JP2001332619A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of a semiconductor device when forming in it a wiring having a dual damascene structure, by so suppressing the expansion of the trench of the wiring as to make possible its high integration extent, and by making possible the formation of a highly reliable wiring. SOLUTION: A manufacturing method of the semiconductor device has a process for forming first and second insulation films 12, 15 on a substrate 11, a process for forming on the second insulation film 15 a first under-mask layer 21 having a formed hole-pattern for forming a connection hole, a process for forming on the first under-mask layer 21 a second mask layer 22 having a formed trench-pattern 23 for forming a wiring trench, a process for so forming a first over-mask layer 24 by burying in the trench pattern 23 the same kind of material as the first under-mask layer 21 as to form a first mask layer 25 together with the first under-mask layer 21, and a process for so forming in the first mask layer 25 a hole pattern 27 that at least a portion of the hole pattern 27 overlaps with the trench pattern 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a dual damascene structure is formed using a so-called dual hard mask.

[0002]

2. Description of the Related Art There are three methods for forming a dual damascene structure using a two-layer hard mask.

A first conventional manufacturing method is a method for forming a dual damascene structure on a silicon oxide-based interlayer insulating film. This first conventional manufacturing method will be described with reference to a manufacturing process sectional view of FIG.

As shown in FIG. 4A, a barrier layer 112, a connection layer 113, an intermediate etching stopper layer 114, and a wiring layer 115 are sequentially formed on a substrate 111. The base 111 is formed, for example, by forming elements, wirings and the like (not shown) on a substrate (not shown), and forming an insulating film 131 covering these elements, wirings and the like. The barrier layer 112 is formed, for example, by depositing a silicon nitride film to a thickness of 50 nm. The connection layer 113 is, for example, a silicon oxide film of 500 n.
It is formed by depositing to a thickness of m. The intermediate etching stopper layer 114 is formed by depositing, for example, a silicon nitride film to a thickness of 100 nm. The wiring layer 115 is formed, for example, by depositing a silicon oxide film to a thickness of 300 nm.

Next, a lower hard mask 121 is formed on the wiring layer 115 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, an upper hard mask 122 is formed on the lower hard mask 121 by, for example,
It is formed by depositing to a thickness of nm. Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Then
A groove pattern 123 for forming a wiring groove in the upper hard mask 122 using the resist film as an etching mask.
To form After that, the resist film is removed.

Next, as shown in FIG. 4B, a resist film 124 is formed by a resist coating technique so as to cover the upper hard mask 122 and the groove pattern 123, and then the resist film 12 is formed by a lithography technique.
4, a hole pattern 125 for forming a connection hole is formed.

Next, as shown in FIG. 4C, a hole pattern 125 is extended in the lower hard mask 121 by etching using the resist film 124 as a mask. Further, as shown in FIG.
4 as a mask, the wiring layer 115 is etched.
The hole pattern 125 is formed by extension. Further, as shown in FIG. 4 (5), the intermediate etching stopper layer 114
The hole pattern 125 is formed by extension. After that, the resist film 124 (see FIG. 4 (4)) is removed.

Next, as shown in FIG. 4 (6), a groove pattern 123 is formed in the lower hard mask 121 by using the upper hard mask 122 as an etching mask, and a wiring groove 116 is formed in the wiring layer 115. Is formed, and a connection hole 117 is formed in the connection layer 113 using the intermediate etching stopper layer 114 as an etching mask.

Next, as shown in FIG. 4 (7), the upper hard mask 122 (see FIG. 4 (6)) is removed. At this time, the intermediate etching stopper layer 114 exposed at the bottom of the wiring groove 116 is removed by etching.
16 is extended and the barrier layer 112 exposed at the bottom of the connection hole 117 is removed by etching.
17 is extended.

According to a second conventional manufacturing method, a non-doped silicate glass (NS) having a relative dielectric constant of about 4.0 of silicon oxide is used for an inter-wiring insulating film (connection layer) in which a connection hole is formed.
G), phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), or fluorine phosphorus silicate glass (FSG) having a relative dielectric constant of about 3.5, and an organic film is used as an insulating film (wiring layer) between wiring layers. Is a method of forming a dual damascene structure using a polyarylether having a relative dielectric constant of about 2.7. This second conventional manufacturing method will be described with reference to a manufacturing process sectional view of FIG.

As shown in FIG. 5A, a barrier layer 112, a connection layer 113, and a wiring layer 115 are sequentially laminated on a base 111. The base 111 is, for example, a substrate (not shown).
An element, a wiring, and the like (not shown) are formed thereon, and an insulating film 131 that covers the element, the wiring, and the like is formed. The barrier layer 112 is formed, for example, by depositing a silicon nitride film to a thickness of 50 nm. The connection layer 113 is formed, for example, by depositing a silicon oxide film to a thickness of 500 nm.
The wiring layer 115 is formed, for example, by depositing an organic film to a thickness of 400 nm.

Next, a lower hard mask 121 is formed on the wiring layer 115 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, the lower hard mask 121
An upper hard mask 122, for example, silicon nitride
It is formed by depositing to a thickness of 00 nm. Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Next, a groove pattern 123 for forming a wiring groove is formed in the upper hard mask 122 using the resist film as an etching mask. After that, the resist film is removed.

Next, as shown in FIG. 5B, after forming a resist film 124 by a resist coating technique so as to cover the upper hard mask 122 and the groove pattern 123, the resist film 12 is formed by a lithography technique.
4, a hole pattern 125 for forming a connection hole is formed.

Next, as shown in FIG. 5C, by etching using the resist film 124 as a mask,
A hole pattern 125 is formed in the lower hard mask 121 by extension. Further, as shown in FIG.
The hole pattern 125 is extended in the wiring layer 115 by etching using 24 (see FIG. 5C) as a mask. At this time, the resist film 124 is also removed by etching. Therefore, the lower hard mask 121 has a function as an etching mask from the middle of the etching. Further, as shown in FIG. 5 (5), a groove pattern 123 is formed in the lower hard mask 121 using the upper hard mask 122 as an etching mask, and connected to the connection layer 113 using the wiring layer 115 as an etching mask. A hole 117 is formed.

Next, as shown in FIG. 5 (6), the wiring groove 11 is formed in the wiring layer 115 by using the upper hard mask 122 and the lower hard mask 121 as an etching mask.
6 is formed.

Next, as shown in FIG. 5 (7), the upper hard mask 122 (see FIG. 5 (6)) is removed. At this time, the etching of the bottom of the wiring groove 116 is stopped by the connection layer 113, and the barrier layer 112 exposed at the bottom of the connection hole 117 is removed by etching.
7 is extended.

A third conventional manufacturing method is a method of forming a dual damascene structure on an organic interlayer insulating film. This third conventional manufacturing method will be described with reference to the manufacturing step sectional views of FIGS.

As shown in FIG. 6A, a barrier layer 112, a connection layer 113, an intermediate etching stopper layer 114, and a wiring layer 115 are sequentially formed on a substrate 111. The base 111 is formed, for example, by forming elements, wirings and the like (not shown) on a substrate (not shown), and forming an insulating film 131 covering these elements, wirings and the like. The barrier layer 112 is formed, for example, by depositing a silicon nitride film to a thickness of 50 nm. The connection layer 113 is formed, for example, by depositing an organic film to a thickness of 400 nm. Intermediate etching stopper layer 1
14 is formed, for example, by depositing a silicon oxide film to a thickness of 100 nm. The wiring layer 115 is, for example, an organic film of 400
It is formed by depositing to a thickness of nm.

Next, a lower hard mask 121 is formed on the wiring layer 115 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, the lower hard mask 121
An upper hard mask 122, for example, silicon nitride
It is formed by depositing to a thickness of 00 nm. Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Next, a groove pattern 123 for forming a wiring groove is formed in the upper hard mask 122 using the resist film as an etching mask. After that, the resist film is removed.

Next, as shown in FIG. 6B, a resist film 124 is formed by a resist coating technique so as to cover the upper hard mask 122 and the groove pattern 123, and then the resist film 124 is formed by a lithography technique. Then, a hole pattern 125 for forming a connection hole is formed.

Next, as shown in FIG. 6C, by etching using the resist film 124 as a mask,
The hole pattern 125 is extended in the lower hard mask 121. Further, as shown in FIG. 6D, the hole pattern 12 is formed in the wiring layer 115 by etching using the resist film 124 (see FIG. 6C) as a mask.
5 is extended. At this time, the resist film 124 is also removed by etching. Therefore, the lower hard mask 121 has a function as an etching mask from the middle of the etching. Further, as shown in (5) of FIG. 6, a groove pattern 123 is formed in the lower hard mask 121 by using the upper hard mask 122 as an etching mask, and the intermediate etching stopper layer is formed using the wiring layer 115 as an etching mask. An upper portion of the connection hole 117 is formed at 114.

Next, as shown in (6) of FIG.
Wiring grooves 116 are formed in the wiring layer 115 using the lower hard masks 122 and 121 as an etching mask, and connection holes 117 are formed in the connection layer 113 using the intermediate etching stopper layer 114 as an etching mask.

Next, as shown in FIG. 6 (7), the upper hard mask 122 (see FIG. 6 (6)) is removed. At this time, with the intermediate etching stopper layer 114 serving as an etching mask, the barrier layer 112 exposed at the bottom of the connection hole 117 is removed by etching to extend the connection hole 117.

The organic film used for the wiring layer and the connection layer in the above-mentioned conventional manufacturing method generally has a lower dielectric constant than a silicon oxide-based insulating film, so that the parasitic capacitance of the wiring is reduced and the signal delay is reduced. Can be. Therefore, application to a high-performance semiconductor device is being studied.

[0025]

However, in the first conventional manufacturing method, since the etching selectivity of the upper hard mask with respect to the wiring layer is low, the wiring groove is formed in an enlarged manner. As a result, the wiring groove formed in the wiring layer is formed to be larger than the design dimension.

It is effective to increase the thickness of the upper hard mask in order to prevent the formation of the wiring groove from being enlarged. However, when the upper hard mask is thickened, a lithography process for forming a hole pattern thereafter is effective. Will result in a decrease in resolution.

Therefore, in the photolithography process,
By forming an antireflection film having a thickness of 50 nm to 100 nm on the underlayer of the photosensitive resist film, reflection of light rays from the underlayer is prevented, and the resolution is improved. However, if there is a step when the antireflection film is formed, the antireflection film cannot be formed to a uniform thickness. As a result, the resolution in the photolithography process decreases. In particular, when the step is 100 nm or more, the antireflection film cannot be formed with good coverage. For example, in the step of forming a hole pattern for forming a connection hole in a resist film, the minimum resolution diameter is 0.22 μm when there is a step of 100 nm, and 0.1 mm when there is a step of 200 nm. 25 μm. As described above, the smaller the step, the higher the resolution in the photolithography process. Therefore, in order to stably process a fine hole having a hole diameter of 0.13 μm, it is important to suppress the step to 100 nm or less.

On the other hand, the lithography technology includes an electron beam direct writing lithography technology which is not affected by a step. However, the electron beam direct writing lithography technology is not suitable for mass production because its manufacturing cost is high.

The problem of enlarging the wiring groove becomes larger as the etching amount in the step of forming the wiring groove is larger. 1st, 2nd
In the conventional manufacturing method, the etching amount is about 500 nm.
In the third conventional manufacturing method, the etching amount is about 200 nm. Therefore, in the first and second conventional manufacturing methods, the problem of the enlargement of the wiring groove appears more wisely. When the spread amount Δ of the wiring width was measured based on the actual processing result, Δ = 120 nm in the first and second conventional manufacturing methods, and Δ = 40 nm in the third conventional manufacturing method. . For example, if the wiring pitch is 400 nm (wiring width is 200
In order to form a wiring with a wiring interval of 200 nm (nm and a wiring interval of 200 nm), the width of the wiring is required to be suppressed to 5% or less of the wiring width, that is, to 10 nm or less in the above example. Therefore, it becomes difficult to apply the first to third conventional manufacturing methods.

When the wiring grooves are formed in an enlarged manner, adjacent wiring grooves are connected to each other. Therefore, when a wiring is formed by embedding a conductive material in the wiring grooves, adjacent wirings are short-circuited. As a result, short-circuit failure may occur. Also,
If the lithography accuracy is reduced, it becomes difficult to form a pattern of the intended size at the intended position, so that connection failure and short-circuit failure are more likely to occur.

[0031]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film having a connection hole formed on a base;
A step of forming a second insulating film in which a wiring groove is formed on the first insulating film, and a first mask in which a hole pattern for forming a connection hole is formed on the second insulating film Forming a lower layer, forming a second mask layer having a groove pattern for forming a wiring groove on the first mask lower layer, and forming the first mask lower layer in the groove pattern. A step of forming a first mask upper layer by embedding the same kind of material to form a first mask layer by the first mask lower layer and the second mask upper layer, and at least partially overlapping the groove pattern Forming a hole pattern in the first mask as described above.

In the method of manufacturing a semiconductor device, a material similar to that of the first mask lower layer is embedded in the groove pattern to form a first mask upper layer, and the first mask lower layer and the second mask are formed. Since the step of forming the first mask layer with the upper layer is provided, even if the thickness of the second mask layer of the upper mask is increased, the surfaces of the first and second mask layers remain flat. That is, it is possible to reduce the level difference of the second mask layer, which has occurred in the conventional manufacturing method. Therefore, in the lithography step when forming a hole pattern in the first mask layer, it becomes possible to form a resist film on the planarized first and second mask layers and perform the lithography step.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to a cross-sectional view of a manufacturing process in FIG.

As shown in FIG. 1A, a barrier layer 13 and a connection layer 14 are formed as a first insulating film 12 on a substrate 11 in order from the lower layer. Further, on the first insulating film 12,
Intermediate etching stopper layer 16 as second insulating film 15
And the wiring layer 17 are sequentially laminated from the lower layer. The base 11 is formed, for example, by forming elements, wirings and the like (not shown) on a substrate (not shown), and forming an insulating film 31 covering these elements, wirings and the like. The barrier layer 13 is formed, for example, by depositing a silicon nitride film to a thickness of 50 nm.
The connection layer 14 is formed, for example, by depositing a silicon oxide film to a thickness of 500 nm. Intermediate etching stopper layer 16
Is formed, for example, by depositing a silicon nitride film to a thickness of 100 nm. The wiring layer 17 is made of, for example, 30
It is formed by depositing to a thickness of 0 nm.

Next, a first mask lower layer 21 is formed as a lower hard mask on the second insulating film 15 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, a second mask layer 22 serving as an upper hard mask is formed on the first mask lower layer
It is formed by depositing to a thickness of nm. This second mask layer 2
2 needs to be formed to be thicker than 100 nm, and is desirably formed to a thickness of 150 nm to 250 nm. By forming the second mask layer 22 to the above thickness, sufficient etching resistance as an etching mask is secured. Note that since the second m-th mask layer 22 is formed of silicon nitride having a relatively high relative dielectric constant, it is preferable that the second m-th mask layer 22 is finally removed. However, if the second mask layer 22 is formed thicker than 250 nm, it becomes difficult to remove the second mask layer 22 in an etching step performed after forming the wiring groove and the connection hole.

Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Next, using the resist film as an etching mask, the second mask layer 22 is formed.
Then, a groove pattern 23 is formed. After that, the resist film is removed.

As shown in FIG. 1B, a first mask upper layer 24 for burying the groove pattern 23 is formed on the second mask layer 22 by depositing, for example, a silicon oxide film to a thickness of 400 nm. I do. Thereafter, the first mask upper layer 24 is polished and removed by chemical mechanical polishing until the surface of the second mask layer 22 is exposed, leaving the first mask upper layer 24 inside the groove pattern 23. As a result, a first mask layer 25 is formed by the first mask upper layer 24 and the first mask lower layer 21. In the drawings, the state after polishing is shown.

Next, as shown in FIG. 1 (3), a resist film 26 is formed by a resist coating technique so as to cover the second mask layer 22 and the first mask layer 25.
Is formed, a hole pattern 27 for forming a connection hole in the resist film 26 is formed by a lithography technique.

Next, as shown in FIG. 1D, the hole pattern 27 is extended in the first mask layer 25 by etching using the resist film 26 as a mask. Further, as shown in FIG. 1 (5), the wiring layer 1 is etched by using the resist film 26 as a mask.
7, the hole pattern 27 is extended. Further, FIG.
(6), the intermediate etching stopper layer 16
The hole pattern 27 is formed as an extension. Thereafter, the resist film 26 [see (5) in FIG. 1] is removed.

Next, as shown in FIG. 1 (7), a groove pattern 23 is formed in the first mask layer 25 using the second mask layer 22 as an etching mask. Further, a wiring groove 18 is formed in the wiring layer 17. With it,
A connection hole 19 is formed in the connection layer 14 using the intermediate etching stopper layer 16 as an etching mask.

Next, as shown in FIG. 1 (8), the second mask layer 22 [see FIG. 1 (7)] is removed. At this time, the intermediate etching stopper layer 16 exposed at the bottom of the wiring groove 18 is removed to extend the wiring groove 18, and the barrier layer 13 exposed at the bottom of the connection hole 19 is removed to form the connection hole 19. Form extension.

In the first embodiment, the groove pattern 2
3 is filled with the same material as the first mask lower layer 21 to form a first mask upper layer 24, and the first mask lower layer 2 is formed.
Since the first and second mask upper layers 24 include a step of forming the first mask layer 25, the second mask layer 22
Even if the film thickness is increased, the surfaces of the first and second mask layers 25 and 22 are flattened, and the step of the second mask layer 22 caused by the conventional manufacturing method can be reduced or eliminated. Will be possible. Therefore, in the lithography process when forming the hole pattern 27 in the first mask layer 25, the resist film 26 is formed on the planarized first and second mask layers 25 and 22, and the lithography process is performed. It becomes possible. Furthermore, since the thickness of the second mask layer 22 can be increased, it is possible to suppress the retreat of the second mask layer 22 that has occurred when the wiring groove 18 is formed. Expansion is reduced.

The second method according to the method for manufacturing a semiconductor device of the present invention.
The embodiment will be described with reference to the manufacturing process sectional views of FIG.

As shown in FIG. 2A, a barrier layer 13 and a connection layer 14 are formed as a first insulating film 12 on a substrate 11 in order from the lower layer. Further, on the first insulating film 12,
A second insulating film 15 is formed. The base 11 is formed, for example, by forming elements, wirings and the like (not shown) on a substrate (not shown), and forming an insulating film 31 covering these elements, wirings and the like. The barrier layer 13 is, for example, a silicon nitride film of 50
It is formed by depositing to a thickness of nm. The connection layer 14 is formed, for example, by depositing a silicon oxide film to a thickness of 500 nm. The second insulating film 15 is formed by depositing, for example, an organic film to a thickness of 400 nm.

Next, a first mask lower layer 21 is formed on the second insulating film 15 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, a second mask layer 22 is formed on the first mask lower layer 21 by, for example, silicon nitride.
It is formed by depositing to a thickness of 00 nm. The second mask layer 22 needs to be formed thicker than 100 nm, and is desirably formed to a thickness of 150 nm to 250 nm. With this thickness, sufficient etching resistance as an etching mask is ensured. In addition,
Since the second mask layer 22 is formed of silicon nitride having a relatively high relative dielectric constant, it is desirable that the second mask layer 22 is finally removed. However, the second mask layer 22 is
If it is formed thicker than nm, it becomes difficult to remove it in an etching step performed after forming the wiring groove and the connection hole.

Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Next, using the resist film as an etching mask, the second mask layer 22 is formed.
Then, a groove pattern 23 is formed. After that, the resist film is removed.

As shown in FIG. 2B, a first mask upper layer 24 for embedding the groove pattern 23 is formed on the second mask layer 22 by depositing, for example, a silicon oxide film to a thickness of 400 nm. I do. Thereafter, the first mask upper layer 24 is polished and removed by chemical mechanical polishing until the surface of the second mask layer 22 is exposed, leaving the first mask upper layer 24 inside the groove pattern 23. As a result, a first mask layer 25 is formed by the first mask upper layer 24 and the first mask lower layer 21. In the drawings, the state after polishing is shown.

Next, as shown in FIG. 2 (3), a resist film 26 is formed by a resist coating technique so as to cover the second mask layer 22 and the first mask layer 25.
Is formed, a hole pattern 27 for forming a connection hole in the resist film 26 is formed by a lithography technique.

Next, as shown in FIG. 2D, the hole pattern 27 is extended in the first mask layer 25 by etching using the resist film 26 as a mask. Further, as shown in FIG. 2 (5), the hole pattern 27 is extended in the second insulating film 15 by etching using the resist film 26 (see FIG. 2 (4)) as a mask. . At this time, the resist film 26, which is an organic film, is also etched away. Therefore, the first mask layer 25 functions as an etching mask during the etching. Therefore, there is no need to perform the step of removing the resist film 26. Further, as shown in (6) of FIG. 2, the groove pattern 23 is opened again in the second mask layer 22 using the second mask layer 22 as an etching mask. Further, a groove pattern 23 is formed in the first mask layer 25 so as to be extended. At the same time, the second insulating film 15
Is used as an etching mask to form a connection hole 19 in the connection layer 14.

Next, as shown in FIG. 2 (7), using the second mask layer 22 and the first mask layer 25 as an etching mask, a wiring groove 18 is formed in the second insulating film 15.
To form

Next, as shown in FIG. 2 (8), the second mask layer 22 (see FIG. 2 (7)) is removed. At this time, the connection layer 14 exposed at the bottom of the wiring groove 18 functions as an etching mask, and the barrier layer 13 exposed at the bottom of the connection hole 19 is removed by etching.

In the second embodiment, the groove pattern 2
3 is filled with a material similar to that of the first mask lower layer 21 to form a first mask upper layer 24, and the first mask lower layer 21 is formed.
And a step of forming the first mask layer 25 with the second mask upper layer 24. Therefore, even if the thickness of the second mask layer 22 is increased, the first and second mask layers 25 and 22 are formed. The surface is in a flattened state, and it is possible to reduce or eliminate the step of the second mask layer 22 caused by the conventional manufacturing method. Therefore, in the lithography process when forming the hole pattern 27 in the first mask layer 25, the resist film 26 is formed on the planarized first and second mask layers 25 and 22, and the lithography process is performed. It becomes possible. Furthermore, since the thickness of the second mask layer 22 can be increased, it is possible to suppress the retreat of the second mask layer 22 that has occurred when the wiring groove 18 is formed. Expansion is reduced.

Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the cross-sectional views of the manufacturing process shown in FIG.

As shown in FIG. 3A, a barrier layer 13, a connection layer 14, and an intermediate etching stopper layer 16 are formed as a first insulating film 12 on a substrate 11 in this order from the bottom. Further, a second insulating film 15 serving as a wiring layer is formed on the first insulating film 12. The base 11 is formed by, for example, forming elements, wiring, and the like (not shown) on a substrate (not shown),
An insulating film 31 covering these elements, wirings, and the like is formed. The barrier layer 13 is made of, for example, 50
It is formed by depositing to a thickness of nm. The connection layer 14 is formed, for example, by depositing an organic film to a thickness of 400 nm. The intermediate etching stopper layer 16 is made of, for example, a silicon oxide film.
It is formed by depositing to a thickness of 00 nm. Second insulating film 1
5 is formed, for example, by depositing an organic film to a thickness of 400 nm.

Next, a first mask lower layer 21 is formed on the second insulating film 15 by depositing, for example, silicon oxide to a thickness of 200 nm. Further, a second mask layer 22 is formed on the first mask lower layer 21 by, for example, silicon nitride.
It is formed by depositing to a thickness of 00 nm. The second mask layer 22 needs to be formed thicker than 100 nm, and is desirably formed to a thickness of 150 nm to 250 nm. With this thickness, sufficient etching resistance as an etching mask is ensured. In addition,
Since the second mask layer 22 is formed of silicon nitride having a relatively high relative dielectric constant, it is desirable that the second mask layer 22 is finally removed. However, the second mask layer 22 is
If it is formed thicker than nm, it becomes difficult to remove it in an etching step performed after forming the wiring groove and the connection hole.

Next, after forming a resist film (not shown) by a resist coating technique, a groove pattern (not shown) for forming a wiring groove in the resist film is formed by a lithography technique. Next, using the resist film as an etching mask, the second mask layer 22 is formed.
Then, a groove pattern 23 is formed. After that, the resist film is removed.

As shown in FIG. 3B, a first mask upper layer 24 for embedding the groove pattern 23 is formed on the second mask layer 22 by depositing, for example, a silicon oxide film to a thickness of 400 nm. I do. Thereafter, the first mask upper layer 24 is polished and removed by chemical mechanical polishing until the surface of the second mask layer 22 is exposed, leaving the first mask upper layer 24 inside the groove pattern 23. As a result, a first mask layer 25 is formed by the first mask upper layer 24 and the first mask lower layer 21. In the drawings, the state after polishing is shown.

Next, as shown in FIG. 3C, a resist film 26 is applied by a resist coating technique so as to cover the second mask layer 22 and the first mask layer 25.
Is formed, a hole pattern 27 for forming a connection hole in the resist film 26 is formed by a lithography technique.

Next, as shown in FIG. 3D, the hole pattern 27 is formed in the first mask layer 25 by etching using the resist film 26 as a mask. Further, as shown in FIG. 3 (5), the hole pattern 2 is formed in the second insulating film 15 by etching using the resist film 26 (see FIG. 3 (4)) as a mask.
7 is extended. At this time, the resist film 26, which is an organic film, is also etched away. Therefore, the first mask layer 25 functions as an etching mask during the etching. Therefore, there is no need to perform the step of removing the resist film 26. Further, as shown in (6) of FIG. 3, the groove pattern 23 is opened again in the second mask layer 22 using the second mask layer 22 as an etching mask. Further, a groove pattern 23 is formed in the first mask layer 25 so as to be extended. At the same time, the intermediate etching stopper layer 16 is formed using the second insulating film 15 as an etching mask.
The hole pattern 27 is formed as an extension.

Next, as shown in FIG. 3 (7), using the second mask layer 22 and the first mask layer 25 as an etching mask, a wiring groove 18 is formed in the second insulating film 15. Is formed, and a connection hole 19 is formed in the connection layer 14 using the intermediate etching stopper layer 16 as an etching mask.

Next, as shown in FIG. 3 (8), the second mask layer 22 [see FIG. 3 (7)] is removed. At this time, the barrier layer 13 exposed at the bottom of the connection hole 19 is also etched away using the intermediate etching stopper layer 16 as a mask.

In the third embodiment, the groove pattern 2
3 is filled with a material similar to that of the first mask lower layer 21 to form a first mask upper layer 24, and the first mask lower layer 21 is formed.
And a step of forming the first mask layer 25 with the second mask upper layer 24. Therefore, even if the thickness of the second mask layer 22 is increased, the first and second mask layers 25 and 22 are formed. The surface is in a flattened state, and it is possible to reduce or eliminate the step of the second mask layer 22 caused by the conventional manufacturing method. Therefore, in the lithography process when forming the hole pattern 27 in the first mask layer 25, the resist film 26 is formed on the planarized first and second mask layers 25 and 22, and the lithography process is performed. It becomes possible. Furthermore, since the thickness of the second mask layer 22 can be increased, it is possible to suppress the retreat of the second mask layer 22 that has occurred when the wiring groove 18 is formed. Expansion is reduced.

In each of the above embodiments, the silicon oxide film can be formed using a high-density plasma CVD apparatus capable of flattening a step. Or
Film formation can also be performed using a parallel plate type plasma CVD apparatus. Alternatively, it may be formed by depositing SOG using a spin coating device.

[0065]

As described above, according to the method of manufacturing a semiconductor device of the present invention, even if the second mask layer is made thicker, the surfaces of the first and second mask layers are flattened. Therefore, the step of the second mask layer, which has occurred in the conventional manufacturing method, can be reduced or eliminated. for that reason,
Since a processing margin in a lithography process when forming a hole pattern in the first mask layer can be reduced, miniaturization is possible and high integration can be achieved. Further, since the thickness of the second mask layer can be increased, the retreat of the second mask layer, which has occurred when forming the wiring groove, can be suppressed. can do. Therefore, highly reliable wiring can be formed, and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view showing a first embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a sectional view showing a manufacturing process according to a second embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to a third embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view of a manufacturing process showing a first conventional manufacturing method.

FIG. 5 is a manufacturing process sectional view showing a second conventional manufacturing method.

FIG. 6 is a cross-sectional view of a manufacturing process showing a third conventional manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Base, 12 ... 1st insulating film, 15 ... 2nd insulating film, 18 ... Wiring groove, 19 ... Connection hole, 21 ... 1st mask lower layer, 22 ... 2nd mask layer, 27 ... Hole pattern , 23
... Groove pattern, 24 ... First mask upper layer, 25 ... First mask layer

Claims (4)

[Claims] A step of forming a first insulating film in which a connection hole is formed on a base; a step of forming a second insulating film in which a wiring groove is formed on the first insulating film; Forming a first mask underlayer in which a hole pattern for forming a connection hole is formed on the second insulating film; and forming a groove pattern for forming a wiring groove on the first mask underlayer. A step of forming the formed second mask layer; and embedding a material of the same type as the first mask lower layer in the groove pattern to form a first mask upper layer, thereby forming the first mask lower layer and the first mask lower layer. A step of forming a first mask layer with an upper layer of the mask, and a step of forming a hole pattern in the first mask layer so as to at least partially overlap the groove pattern. Device manufacturing method. 2. The method according to claim 1, wherein the second insulating film is formed by laminating an etching stopper layer and an inter-wiring insulating film, and after forming a hole pattern in the first mask layer, The first mask layer and the second
Further forming the hole pattern in the second insulating film including the etching stopper layer by using the mask layer, and removing the first mask upper layer in the groove pattern and again forming the groove pattern. Forming a wiring groove in the second insulating film using the etching stopper layer as a mask together with the second mask layer, and forming a connection hole in the first insulating film. 2. The method according to claim 1, further comprising the steps of: 3. After forming a hole pattern in the first mask layer, the first mask layer on which the hole pattern is formed and a second mask layer are formed.
Extending the hole pattern in the second insulating film using the mask layer of (a), removing the upper layer of the first mask in the groove pattern, and re-opening the groove pattern; Forming a wiring groove in the first mask layer using the second mask layer; and forming a connection hole in the first insulating film using the second mask and the second insulating film as a mask. And forming a wiring groove in the second insulating film using the second mask as a mask, and using the first insulating film as an etching stopper.
The manufacturing method of the semiconductor device described in the above. 4. The first insulating film is formed by laminating a wiring interlayer insulating film and an etching stopper layer, and after forming a hole pattern in the first mask layer, The first mask layer and the second
Extending the hole pattern in the second insulating film by using the mask layer of (1), the first mask layer having the hole pattern formed thereon and the second mask layer (2).
Further extending the hole pattern including the etching stopper layer in the second insulating film by using the mask layer; and forming a groove pattern in the first mask layer by using the second mask layer. Forming a wiring groove in the second insulating film using the etching stopper layer as a mask together with the second mask layer, and forming a connection hole in the first insulating film; A method for manufacturing a semiconductor device, comprising: