JPS62111538A - 多重分離回路 - Google Patents

多重分離回路

Info

Publication number
JPS62111538A
JPS62111538A JP60251759A JP25175985A JPS62111538A JP S62111538 A JPS62111538 A JP S62111538A JP 60251759 A JP60251759 A JP 60251759A JP 25175985 A JP25175985 A JP 25175985A JP S62111538 A JPS62111538 A JP S62111538A
Authority
JP
Japan
Prior art keywords
circuit
channel number
order group
initial value
group signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60251759A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0523654B2 (enrdf_load_stackoverflow
Inventor
Osamu Kono
修 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60251759A priority Critical patent/JPS62111538A/ja
Publication of JPS62111538A publication Critical patent/JPS62111538A/ja
Publication of JPH0523654B2 publication Critical patent/JPH0523654B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
JP60251759A 1985-11-09 1985-11-09 多重分離回路 Granted JPS62111538A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60251759A JPS62111538A (ja) 1985-11-09 1985-11-09 多重分離回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60251759A JPS62111538A (ja) 1985-11-09 1985-11-09 多重分離回路

Publications (2)

Publication Number Publication Date
JPS62111538A true JPS62111538A (ja) 1987-05-22
JPH0523654B2 JPH0523654B2 (enrdf_load_stackoverflow) 1993-04-05

Family

ID=17227500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60251759A Granted JPS62111538A (ja) 1985-11-09 1985-11-09 多重分離回路

Country Status (1)

Country Link
JP (1) JPS62111538A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7639817B2 (en) 2002-01-30 2009-12-29 Lg Electronics Inc. Method for scrambling packet data using variable slot length and apparatus thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7639817B2 (en) 2002-01-30 2009-12-29 Lg Electronics Inc. Method for scrambling packet data using variable slot length and apparatus thereof

Also Published As

Publication number Publication date
JPH0523654B2 (enrdf_load_stackoverflow) 1993-04-05

Similar Documents

Publication Publication Date Title
US5241602A (en) Parallel scrambling system
CA2192923C (en) Channel multiplex demultiplex method and channel multiplex demultiplex unit
CA1225710A (en) Self-synchronizing scrambler
JPS6410973B2 (enrdf_load_stackoverflow)
CA1206528A (en) Voice encryption and decryption system
CA1281144C (en) Multiplexing apparatus having bsi-code processing and bit interleave functions
JP2850858B2 (ja) Cdma送受信方式
CA1225709A (en) Self-synchronizing descrambler
JPS62111538A (ja) 多重分離回路
US6037884A (en) Technique to encode multiple digital data streams in limited bandwidth for transmission in a single medium
JPH0275240A (ja) 伝送スクランブル方式
JPS6334663B2 (enrdf_load_stackoverflow)
JP3119956B2 (ja) 多重クロック伝送方法および装置
JPH08331120A (ja) スクランブル符号生成回路
JPH0697756B2 (ja) パルス多重通信方式
JP2988120B2 (ja) ディジタル送信装置,ディジタル受信装置およびスタッフ同期多重伝送装置
JP2692476B2 (ja) フレーム同期システム
JP2674799B2 (ja) 高能率ディジタル分岐挿入装置
JPH0683204B2 (ja) スクランブル・デスクランブル方式
JP2581240B2 (ja) 多重化装置
JPH0732379B2 (ja) 擬似同期防止回路
JP3248503B2 (ja) 時分割多重回路及び時分割多重方法
JP2671803B2 (ja) データ多重伝送装置
JPH0234538B2 (enrdf_load_stackoverflow)
JPH05268581A (ja) 高速多重化方式