JPS62111538A - Multiplex separation circuit - Google Patents

Abstract

PURPOSE:To keep the scramble effect at a high order group signal by adding a circuit converting a channel number to an initial value of a scramble circuit to the transmission and reception side so as to eliminate the need for the transmission of an initial value by an overhead bit. CONSTITUTION:A channel number 102 is converted into an initial value 103 of a scramble circuit 1 by a generating circuit 3, set to the circuit 1, a low order group data 101 is converted into a pseudo random pattern by the circuit 1, after the channel number is inserted to the overhead bit at a channel number insertion circuit 3, the result is multiplexed into a high order group signal 105 by an m-bit shift register 4. In a separation section, the low order group signal 104 obtained by an m-bit shift register 9, a channel number separation circuit 10 and an mXm selector 8 is given to a separation circuit 6, and the separated channel number is converted into an initial value 103 of a descrambler circuit 5 by the generating circuit 3 and set to the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a demultiplexing circuit, and more particularly to a scrambling method in a synchronous multiplex converter.

Conventional technology In a synchronous network in which all clocks in the network are synchronized with a reference clock, a method has been proposed to simplify the demultiplexing circuit. As -ν1j of such a method, for example, Bell Technical Advisory (Bell Technical Advisory)
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That is, on the multiplexing side, as shown in FIG. Insert it and use it as a low-order group signal/well. Next, 70 m low-order group signals are transferred to 10 high-order group signals by an m-bit shift register.
multiplexed into S. On the separation side, as shown in FIG. 1(b), the high-order group signal lθ is converted into m low-order group signals by the m-bit shift register 9 and output from each stage of the shift register. Among these, the low-order group signals of the /th stage are supplied to the channel number separation circuit 10, where 10 channel numbers (or bits) are separated. Separation is completed by controlling mxm selector t using this channel number 10. Thereafter, the separated low-order group signal is converted into the original low-order group data symbol by a descrambler circuit S.

In such a multiplexing/demultiplexing circuit, scrambling is performed on low-order group signals, so that the scrambling effect is reduced on high-order group signals. That is, Figure 1 (a)
If the low-order group input data signals 70 in 2 have the same pattern in phase, the scrambled low-order group signal 1014 also has the same pattern in phase, and the high-order group signal 10S has m identical patterns. The codes will be consecutive.

Problem to be Solved by the Invention In order to solve this problem, it is necessary to set the scrambler circuits to different initial values.

On the transmitting side, as shown in Figure 1 (a), the initial value /Q is set in the scrambler circuit l, and at the same time, the overhead bit insertion circuit ? An initial value is inserted in the IC, and on the receiving side, as shown in FIG. 1(b), the initial value is separated 1. ．． 1. Add seven bits to the descrambler circuit. FIG. 3 shows an example of a frame structure including a channel number (ID bit) and initial values (SF, ED bits) of the scrambler circuit as overhead bits.

Thus, in the conventional system, it was necessary to transmit the initial value using overhead bits.

The present invention has been developed in view of the above-mentioned conventional circumstances.Accordingly, an object of the present invention is to eliminate the need for transmitting initial values by overhead pits, and to maintain the scrambling effect in high-order group signals. The purpose of this paper is to propose a new demultiplexing circuit.

Means for Solving the Problems In a multiplexing system in which m-channel low-order group signals are bit-multiplexed by m-bit shift registers.

It is necessary to transmit the channel number.

The demultiplexing circuit according to the present invention is configured by adding a circuit for converting a channel number using the initial value of the scrambler circuit to the transmitting side and the receiving side, thereby eliminating the need for transmitting the initial value. It has particular characteristics.

Since the channel number is different for each channel, it is possible to generate a different initial value for the scrambler circuit for each channel. In this way, even if the same in-phase pattern is input to each channel, the phases of the patterns output from the scrambler circuit are different, so that a scrambling effect can be produced on the higher-order group signal.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 (b) shows an embodiment of a demultiplexing circuit according to the present invention.

The operation of the multiplexing section in FIG. 1(a) is as follows.

Channel number 10 is supplied to the initial value generation circuit 3,
It is converted to the initial value 103 of the scrambler circuit and set in the scrambler circuit. The low-order group data signal 10 is converted into a pseudo-random pattern by the scrambler circuit, and the channel number is inserted into the overhead bits by the channel number insertion circuit, after which the high-order group signal (by the m-bit shift register≠) 105 multiplexed.

Of the portion 6i in FIG. 1(b), the operations of the cobit shift register q5, channel number separation circuit #7, and mXm selector g are similar to the conventional circuit shown in FIG. 1(b). m
The low-order group signal 1o4t outputted from the Xm selector is supplied to a channel number separation circuit B, where the channel numbers are separated. The channel number is converted into an initial value 103 of the descrambler circuit by the initial value generation circuit 3, and set in the descrambler circuit S.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, by using a method of multiplexing scrambled m-channel low-order group signals into a high-order group signal with a clock frequency of m times, the initial value of the scrambling circuit is determined by overhead bits. Even without transmitting
It is possible to construct a demultiplexer circuit that produces a scrambling effect on higher-order group signals.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are block diagrams showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional circuit configuration, and FIG. 3 is a channel arrangement of high-order group signals and a low-order group frame. It is a figure showing an example of composition. /...Scrambler circuit, Co...Channel number insertion circuit, 3...Initial value generation circuit, G...m-bit shift register, S...Descrambler circuit, 6...Channel number separation circuit , ri...overhead bit insertion circuit, g...mXm selector, 9...m-bit shift register, 10...channel number separation circuit, /c...
Initial Value Separation Circuit Patent Applicant NEC Corporation Representative Patent Attorney Yutabe Kumagai (O) 9 Children Mehibe Figure 2

Claims (1)

[Claims] m with the channel number inserted as an overhead bit
In a circuit that multiplex-converts a low-order group signal of a channel into a high-order group signal with a clock frequency m times, the transmitting side includes a scrambler circuit that converts an input low-order group data signal into a random pattern, and a scrambler circuit that converts the channel number into a random pattern. an initial value generation circuit that converts the initial value of the blur circuit; A demultiplexing circuit comprising: an initial value generation circuit that converts a channel number separated from the low-order group signal into an initial value of the descrambler circuit.