JPS62105258A - Direct memory access system - Google Patents

Abstract

PURPOSE:To access other input/output device and a memory device by disconnecting a signal bus part before a direct memory access device operates and connecting the signal bus part and a central processor at the end of the operation. CONSTITUTION:When data needs to be transferred between the memory device 6 and an input/output device 7, a central controller 1 operates a signal bus disconnecting device 5 at the end of access to the devices 6 and 7 when accessing them or instantaneously when not to disconnect signal buses 2 and 13 and informing an access controller 8 of that. When the data transfer between the devices 6 and 7 is completed, the access controller 8 informs the central controller 1 of th completion. The central controller 1 which receives it finishes the operation of the signal bus disconnecting device 5 and connects the signal bus parts 2 and 13 again.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a direct memory access method.

[Conventional technology]

In the conventional direct memory access method, the direct memory access controller sends a signal bus clearance request signal to the central controller, and after the central controller finishes the current process, the direct memory access controller uses the signal bus. It is designed to send back a confirmation signal indicating that it is OK to do so.

[Problem that the invention seeks to solve]

In the conventional direct memory access method described above, if the central control unit has only one signal bus, processing via the signal bus is impossible during direct memory access, so the input/output is controlled by the direct memory access control device. In addition to the input/output devices and memory devices that are being executed, it is also impossible to access other input/output devices and memory devices connected to the signal bus, effectively stopping the operation of the central control unit. There was a problem with it.

An object of the present invention is to provide a direct memory access method that solves the above-mentioned problems.

[Means for solving problems]

The present invention provides a central control device having one system of signal bus lines;
It has an input/output device, a memory device, and a direct memory access control device connected to the signal bus, and data transfer between the input/output device and the memory device is executed under the control of the direct memory access control device. In the direct memory access method in the system, a signal bus disconnection device is provided to disconnect the central control device from a signal bus portion to which the input/output device, the memory device, and the direct memory access control device are connected. The signal bus section is separated by a disconnection device before the direct memory access control device starts operating, and the signal bus section and the central control device are connected when the direct memory access control device ends the operation. [Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

First, the configuration of this embodiment will be explained.

A central control device 1 is provided, which device 1 is connected via a signal bus 2 to a memory device 3 and an input/output device 4 . On the other hand, data is transferred between the memory device 6 and the input/output device 7 by a direct access memory method, and the direct memory access control device 8 controls the data transfer.

The memory device 6, the input/output bag W7, and the direct memory access control bag W8 are connected to each other at the signal bus section 13, and further connected to the signal bus 2 via the signal bus disconnection device 5. The signal bus disconnection device 5 is controlled by a signal bus disconnection device control line 9 from the input/output device 4. Furthermore, a signal bus spacing request signal line 10, a spacing request confirmation signal line 11, and a direct memory access end signal line 12 are connected between the input/output device 4 and the direct memory access control device 5.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

When the direct memory access control device 8 is inactive, the signal bus disconnection device 5 controlled by the signal bus disconnection control line 9 connects both signal buses 2 and 13. In this state, access from the central control unit 1 to the memory device 6 and the input/output device 7 is possible. When it becomes necessary to transfer data between these memory groups@6 and the input/output device 7, the direct memory access control device 8 transfers data via the signal bus clearance request signal line 10 and the input/output device 4.
The central controller 1 is notified of the start of direct memory access, and a confirmation signal from the central controller 1 is awaited.

If the central control unit 1 is in the process of accessing the memory device 6 and the input/output device 7, it disconnects the signal bus as soon as the access ends, or immediately if it is not accessing the input/output device 4 and the signal bus disconnection device via the signal bus disconnection device control line 9. operate the device 5;
The signal bus 2 is separated from the signal bus 13. At the same time, the signal bus section 13 is connected to the direct memory access control device 8 through the input/output device 4 and the clearance request m recognition signal line 11.
will notify you that it has been disconnected.

Since the signal bus 2 is separated from the signal bus section 13, the central controller 1 can access and control the memo IJ device 3 connected to the signal bus 2 even when the direct memory access control device 8 is in operation. It has the ability to continue.

When the data transfer between the memory device 6 and the input/output device 7 is completed, the direct memory access control device 8 notifies the central control device 1 that the direct memory access has ended through the direct memory access end signal line 12 and the input/output device 4. Notice. 4- Upon receiving the signal, the central control unit 1 passes through the input/output device 4 and the signal bus disconnection device control line 9, terminates the operation of the signal bus disconnection device 5, and connects the signal bus 2 and the signal bus section 13 again. .

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a central control unit having one system of signal buses, an input/output device connected to this signal bus, a memory device, and a direct memory access control device. In a direct memory access method in a system in which data transfer between an output device and a memory device is executed under the control of a direct memory access control device, a signal that connects an input/output device, a memory device, and a direct memory access control device. By providing a signal bus disconnection device that separates the bus section from the central control device, disconnecting the signal bus section before the direct memory access control device operates, and connecting the signal bus section and the central control device when the direct memory access control device operation is finished. Even when the direct memory access control device is in operation, the central control device can use signal buses other than the signal bus portion, and has the effect of allowing access to other input/output devices and memory devices.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the direct memory access method of the present invention. 1... Central control device 2... Signal bus 3... Memory device 4... Input/output device 5... Signal bus disconnection device 6... Memory device 7... Input/output device 8...・ Dairef■・Memory access control device 9
... Signal bus disconnection device control line 10 ...
Signal bus clearance request signal line 11 ... Clearance request confirmation signal line 12 ... Direct memory access end signal line 13 ... Signal bus section

Claims (1)

[Claims] (1) It has a central control unit having one system of signal bus lines, an input/output device connected to the signal bus line, a memory device, and a direct memory access control device, and a connection between these input/output devices and the memory device. In a direct memory access method in a system in which data transfer is executed under the control of a direct memory access control device, a signal bus portion to which the input/output device, the memory device, and the direct memory access control device are connected; A signal bus disconnection device for disconnecting from the central control device is provided, and the disconnection device disconnects the signal bus section before the direct memory access control device starts operating, and disconnects the signal bus section when the direct memory access control device ends the operation. A direct memory access method characterized by connecting the busbar section and a central control unit.