JPS61131057A - Serial i/o system - Google Patents

Abstract

PURPOSE:To use a serial interface as a bus, by providing one control line in addition to serial I/O lines for multi-CPU system contained in a microprocessor. CONSTITUTION:A microprocessor 1 having a control function and microprocessors 2 and 3 using serial interfaces respectively perform designed functional processes and necessary data input/output through the serial interfaces. Serial I/O lines 4-7 which connect the microprocessors 1-3 with each other are provided and the serial I/O lines 4 and 5 are used as data input- output lines among the microprocessors 1-3. The serial I/O line 6 is used as a synchronizing clock line. The line 7 is made active by means of output signals of the microprocessors 2 and 3 and used as a control line for informing the microprocessor 1 having a control function of a control request for outputting serial data, when the microprocessors 2 and 3 want to output the serial data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface system between device constituent units of a terminal device, including a car telephone terminal device, which is required to be small and portable.

[Prior art and problems to be solved by the invention] Conventionally, a serial interface has been used as this type of interface, but R823 is the implementation method.
A standard interface such as 2C may be used, or the algorithm may be implemented in software through a general purpose 1/O port of a microprocessor. In the former case, the amount of software required for control by a microprocessor is small, but since it requires a general-purpose LSI prepared for a standard interface, an increase in the amount of hardware is unavoidable. The latter is for performing a serial interface using an unused I/O port prepared for functional operation of the device configuration unit.

Although there was no increase in the amount of hardware, the software load was heavy, and it was difficult to implement a high-speed serial interface, which often caused problems in terms of operating speed.

Recently, as the demand for smaller and more portable devices has increased, in order to meet these demands, it is urgently necessary to make both the hardware and software much smaller than the current size, and a serial interface suitable for this has been eagerly awaited.

An object of the present invention is to provide a serial interface method (ie, a serial r/O method) that fully satisfies the requirements for an interface for such small and portable devices.

[Means for solving problems]

The present invention provides clocks, data inputs, and data outputs for multiple CPUs that have recently been built into microprocessors, in order to realize a serial interface that can operate at high speed and with the smallest hardware and software components. The first method is to use the serial Ih line of the
By installing a program with a line control function in one of the microprocessors, it is possible to convert the serial interface into a bus, and multiple microprocessors can be connected on the same interface line, reducing the number of signal lines compared to the conventional serial interface. Unlike interfaces, it is no longer necessary to prepare one-to-one connections, and one-to-many or many-to-many connections can be made, allowing for expandability.

In addition, the microprocessor with the control function outputs the clock on the serial Ih line, and other microprocessors input and output data in synchronization with this clock, so the algorithm is simple and ensures sufficient reliability for high-speed operation. This is a serial interface method (that is, a serial I/O method) that can be used.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a serial interface according to an embodiment of the present invention. 1 is a microprocessor having a control function, and 2 and 3 are microprocessors that use the serial interface of the present invention, each of which is designed It performs functional processing and inputs and outputs necessary data through the serial interface. 4-7
is the serial I/O that connects the microprocessors 1 to 3 above.
I'll take the line. 4 is a serial input data line when viewed from the microprocessor 1, and is a serial output data line when viewed from the processors 2 and 3. 5 is microprocessor 1
When viewed from the microprocessors 2 and 3, it becomes a serial output data line. Reference numeral 6 denotes a synchronous clock line for data transmitted and received by the serial data lines 4 and 5. This synchronous clock is outputted by the microprocessor 1 and treated as an input signal by the microprocessors 2 and 3. It is assumed that data transmitted and received on the serial data lines 4 and 5 is processed in synchronization with this clock. 7 is a control line that activates this signal line with its output signal when the microprocessors 2 and 3 want to output serial data, and notifies the microprocessor 1, which has a control function, of a control request for serial data output. .

As can be seen from Figure 1, microprocessor expansion a
This can be easily done by connecting a microprocessor having the same software as the serial interface software built into the microprocessor 2 or 3 to the 7 real I/O lines 4-7.

Next, using the timing chart in FIG.

The operation of serial I/O lines 4 to 7 in FIG. 1 will be explained.

The following description will be made assuming that the signal on the serial input data line 4 is SI, the signal on the serial output data line 5 is SO1, the signal on the synchronous clock line 6 is SCK, and the signal on the control line 7 is REQ. Further, in the embodiment shown in FIG. 1, a maximum of 16 microprocessors can be connected, and the explanation will be given assuming that the maximum number of bytes of serial data transfer between microprocessors is 16 bytes.

In Fig. 2, the serial output data SO is performed as one frame of 8 bits, and the synchronous clock SCK is the serial output data S at its rising edge.
Eight pieces are sent out at such a timing that it is only necessary to sample O. Figure 2 is.

A case is shown in which data is transferred from a microprocessor 1 having a control function to a microprocessor 2 or 3. In this case, the control line REQ remains inactive and no data signal is generated in the serial input data SI. Data transfers are sent to both microprocessors 2 and 30 via serial output data SO. The microprocessors 2 and 3 constantly receive the serial output data SO, and use the control algorithm shown below to determine whether the data signal is necessary for them and whether or not to incorporate it into the microprocessors 2 and 3. That is, as a transfer procedure, the microprocessor 1 sends the 8
The bit data includes the transfer destination ID number 8 and the number of transferred bytes 9.
In this embodiment, 8 and 9 each have 4 bits. From the next frame, the number of data indicated in the first frame is sent out as serial output data SO using the synchronous clock SCK. This sent data is shown at /O in FIG. When sending data to multiple processors, perform one or more operations as many times as necessary. Further, when sending the same data signal to all connected microprocessors, this can be done by assigning in advance a number corresponding to the contents of the ID number 9 to be sent in the first frame.

Next, an algorithm for sending data from the microprocessor 3 to the microprocessor 1 having a control function will be explained using the timing chart of FIG. In FIG. 3, when the microprocessor 3 activates the control line REQ as a request to send data, the microprocessor 1, which has a control function, recognizes this and polls to see which microprocessor is issuing the data send request. , First, a send request confirmation signal 11 is sent to the microprocessor 2 to the serial data output So. The reason why the signal 11 is sent to the microprocessor 2 first is because its ID number is younger than that of the microprocessor 3.

After sending out the sending confirmation signal 11, it is checked whether the microprocessor with the ID number 7 has issued a sending request for the serial input data SI by sending out 8 pits of the synchronous clock SCK. In FIG. 3, the microprocessor 2 does not receive a transmission request and does not output data to the serial input data SI in synchronization with the synchronous clock SCK. ). Subsequently, the microprocessor 1 similarly sends out a sending request confirmation signal 12t to the microprocessor 3, and then sends out an 8-bit synchronized clock SCK. In this case, since there is a transmission request, the microprocessor 3 outputs the transmission request signal 13 to the serial input data SI. For the transmission request signal 13.

Since the ID number of the microprocessor 3 and the number of bytes to be sent are included as contents, the microprocessor 1 sends out the synchronous clock SCK and receives the data sent from the microprocessor 3 by the number of bytes. When the microprocessor 3 completes sending the data, it makes the control line REQ inactive.

The sending algorithm is terminated by notifying other microprocessors that the sending has ended. The microprocessor 1 with control functions is connected in the manner described above.

One-to-many connections are possible since data sent from multiple microprocessors can be received.

Next, as another embodiment, a case where data is sent from the microprocessor 2 to the microprocessor 3 will be described with reference to FIG. First, the microprocessor 2 activates the control line REQ in the same manner as described in FIG. 3, and notifies the microprocessor 1 of a sending request. The microprocessor 1 starts polling and sends a send request confirmation signal 14 to the microprocessor 2.

In response, the microprocessor 2 sends a sending request signal 15.
to send to serial input data SI.

Microprocessor 1 can recognize that there is a sending request from microprocessor 2. Furthermore, transmission request signal 15
contains the ID number of the microprocessor 2 and the microprocessor 3, so it can be recognized at the same time that data needs to be transferred from the microprocessor 2 to the microprocessor 3. Next, microprocessor 1 and microprocessor 2 are linked to serial I
Performs switching operation between serial input data SI and serial output data SO of the /O line. In other words, the serial output data SO line, which was previously output by microprocessor 1 with a control function and used as input by microprocessors 2 and 3, can now be used by microprocessor 2 as an output, and microprocessor 1 and 3 can use it as input. so that it can be used as
The serial input data SI line, which microprocessor 1 used as an input and microprocessors 2 and 3 used as output, can be switched so that microprocessor 2 can input and use it, and microprocessors 1 and 3 can use it as output. It is done.

After that, the microprocessor 1 uses the synchronous clock SCK.
When the microprocessor 2 sends 8 bits of data, the microprocessor 2 sends a signal 16 containing the ID number of the destination and the number of bytes to be sent to the serial output data SO.

This allows the microprocessor 3 to receive data. Since the microprocessor 1 can recognize the destination ID number and the number of bytes to be sent of the signal 16 by switching the serial I/O line, it sends out synchronous clocks SCK corresponding to the number of bytes.

After microprocessor 2 transfers data to microprocessor 3, microprocessor 2 finishes sending data, switches serial I/O lines SI and SO to their original states, and makes control line REQ inactive. After confirming that it has been returned, the sequence is completed by switching based on the SI and SO of the serial line. Although the algorithm shown in Fig. 4 above is slightly different from the one explained in Fig. 3, in this case, although the hardware configuration is exactly the same, the data is transmitted by microprocessors that do not have control functions. Since transfer is also possible, many-to-many connections can also be realized.

〔Effect of the invention〕

As explained above, the present invention provides serial I/O for the multi-CPU system built into a microprocessor.
By adding one control line in addition to the O line, it is possible to convert the serial interface into a bus, thereby realizing an extensible serial interface with the least amount of hardware and software.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially showing an embodiment of the present invention, FIG. 2 is a timing chart showing an example of how the serial I/O line shown in FIG. 1 is used, and FIG. 3 is similar to FIG. a timing chart showing another usage example of the serial I/O line shown;
FIG. 4 is a timing chart showing yet another usage example of the serial I/O line shown in FIG. 1. 1...Microprocessor with control function. 2... Microprocessor (1) connected to the serial I/O line, 3... Microprocessor (2) connected to the serial I/O line, 4... Serial input data line. 5... Serial output data line, 6... Synchronous clock line. 7...Control line, 8...ID in serial output data
4 bits indicating the number, 9...4 bits indicating the number of bytes to be sent in the serial output data, /O...data transferred using the serial output data, 11...transmission request confirmation signal (1) , 12... Sending request confirmation signal (2
). 13... Transmission request signal, 14... Transmission request confirmation signal. 15... Send request signal, 16... Serial output data including the ID number of the destination and the number of bytes to be sent. Figure 1 Figure 2 REQ□

Claims (1)

[Claims] 1. In a serial interface for a multi-CPU system in a device configuration of a terminal device having a plurality of microprocessors, the multi-CPU processor uses serial I/O lines for clock, data input, and data output. One of them is loaded with a program to control the serial I/O line, and one of the
By adding a control line for controlling in addition to the O line, the serial I/O line can be made into a bus and shared by the control line and the microprocessor having the control function, and A plurality of microprocessors connected by a serial interface other than the microprocessor having the control function constantly receive data, and when transmitting data, activate the control line to connect the microprocessor to the microprocessor having the control function. The serial interface is characterized in that the serial interface is used as a bus by notifying a processor of a transmission request and causing the microprocessor having the control function to control the serial interface, and then transmitting data. O method. 2. Among the serial I/O lines, the clock is output by the microprocessor having the control function, other microprocessors treat it as an input, and data input and output to the serial I/O lines are synchronized with the clock. A serial I/O method according to claim 1, which is carried out by: 3. When sending data from a microprocessor other than the microprocessor with the control function to the microprocessor with the control function, the microprocessor with the control function activates the control line to indicate that there is a request for transmission. and causing the microprocessor having the control function to send polling data including ID numbers assigned to the plurality of microprocessors connected to the serial I/O line, thereby activating the control line. When the microprocessor receives polling data for itself, the microprocessor activates the control line to the microprocessor having the control function by sending out a response signal including its own ID number and the number of data to be sent as a response. The microprocessor having the control function receives the transmitted data from the microprocessor that has issued the transmission request by transmitting a clock corresponding to the number of transmitted data. Serial I/O method according to scope 1 or 2. 4. When data is transferred between microprocessors other than the microprocessor having the control function, the microprocessor making the send request activates the control line to notify the microprocessor having the control function that there is a send request. ID assigned by the microprocessor having the control function to the plurality of microprocessors connected to the serial I/O line.
When the microprocessor that sends polling data including a number and activates the control line receives polling data for itself, it sends a response signal containing its own ID number and the ID number of the microprocessor to which the data is to be transferred. By sending, the microprocessor having the control function recognizes the ID number of the microprocessor that activated the control line and the ID number of the microprocessor to which the data is transferred,
Control of the serial I/O line is transferred from the microprocessor having the control function to the microprocessor that activated the control line, and the microprocessor that activated the control line inputs the ID number of the data transfer destination and the number of data to be sent. Notifying the transmission request signal containing the transmission request signal to the transmission destination microprocessor, and causing the microprocessor having the control function to also receive the transmission request signal,
3. The serial I/O system according to claim 1, wherein data is transferred by supplying a clock necessary for data transfer.