JPH0661078B2 - Computer synchronization method - Google Patents

Description

The present invention relates to a computer-to-computer synchronization system of a composite computer system, and particularly to connecting a plurality of computers in multiple stages or in a ring to execute arithmetic processing while synchronizing them. The present invention relates to a synchronization method that is suitable when

[Conventional technology]

FIG. 3 is an example of a complex computer system in which a large number of computers are connected in multiple stages. A large number of computers 11, 12, 13, ... Computers 111, 112, 113, ... 11
Further, a plurality of computers of the fourth stage are connected to the computers 111 of the third stage and the computers 111 of the third stage by communication lines.

FIG. 4 shows an example of a complex computer system in which a large number of computers are connected in a ring.
The computer 111 is connected to the computer 1, and the final computer 1111f is connected to the computer 1 in the same manner, and is connected by a communication line so as to form a ring as a whole.

Conventionally, synchronization between computers in a multistage configuration as shown in FIG. 3 has been realized as follows. For example, the computer 11 has computers 111, 112, 113, ...
Repeat the check until the contents of the memory of the 11m register, or the dedicated sync signal line from each computer and the state of the signal line after taking the wiring logic to the expected value, or the above synchronization Interrupt processing is performed by using the signal line as an interrupt signal line to the computer 11. That is, the computer 11
Then, because it matches the expected value or an interrupt occurs, the computers 111, 112, 113, ... 11
It is detected by software processing that m is synchronized. Further, the computer 11 is the computer 111, 112, 11
3, ... 11m are notified of the synchronization result, and the writing to the memory of these computers and the interrupt function are used to detect changes in the memory contents and the occurrence of interrupts.
At 112, 113, ... 11m, we know that synchronization has been achieved. Furthermore, synchronization of the entire multi-stage computer system is realized by notifying the results of the computers 11, 12, 13, 1n to the computer 1 by the contents of registers and memories or the synchronization signal line. In addition,
The synchronization register and memory are composed of a plurality of bits, the expected value is called a synchronization pattern, and multiple types of synchronization (multi-pattern synchronization) are realized by preparing a plurality of this synchronization pattern.

The case where a large number of computers shown in FIG. 4 are connected in a ring is basically the same as above.

[Problems to be solved by the invention]

As described above, since the conventional synchronization method is via software, even if the time until the actual synchronization is best after all the computers to be synchronized generate the synchronization signal, the machine clock is 10 or more clocks. To tens of clocks. Therefore, when computers are connected in multiple stages, there is a problem that the time required for synchronization greatly affects the performance. In order to shorten the synchronization time, it is possible to configure the software processing by hardware, but in that case, the synchronization time can be shortened, and since the structure is fixed, there are many patterns equivalent to software processing. The problem arises that synchronization cannot be achieved.

It is an object of the present invention to provide a synchronization system that realizes high-speed multi-stage and multi-pattern synchronization among a large number of computers connected in multi-stages or in a ring.

[Means and Actions for Solving Problems]

The present invention, in a composite computer system in which a plurality of computers are connected in a plurality of stages or in a ring, in each computer,
A register for holding the synchronization pattern, a switching circuit for selecting whether to transmit the synchronization pattern held in the register to the next stage or to pass the synchronization pattern transmitted from the previous stage to the next stage, and the next stage A switching circuit for selecting whether to transmit the returned synchronization result to the previous stage or to return the synchronization pattern transmitted from the previous stage to the previous stage as the synchronization result, a holding circuit that holds the state of these switching circuits, and the register And a matching circuit that determines whether or not the synchronization pattern held in step 1 and the synchronization result returned from the next stage match.

When realizing synchronization, each switching circuit is preset to a certain combination in each computer, the synchronization pattern is set in the register, and the synchronization result returned from the next stage is held in the register. The coincidence circuit detects that the synchronization pattern coincides with the existing synchronization pattern, thereby recognizing that synchronization has been established between the entire complex computer system or a plurality of computers to which the synchronization result has propagated.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of an embodiment of the present invention, in which computers 11, 12, and 13 are connected to computer 1, and computer 11
1 shows a three-stage composite computer system in which computers 111, 112, 113 are connected. The synchronization signal bus circuit 26 is a circuit that collectively inputs the synchronization signals from the computers 11, 12, and 13 to the input of the computer 1. The synchronization signal bus circuit 261
Is a circuit that collects the synchronization signals from the computers 111, 112, 113 and inputs them to the computer 11, and normally wired and logic is used. The signal line 27 is a synchronizing signal input line, the signal line 29 is a synchronizing signal output line, and the signal line 2
Reference numeral 8 is a synchronization result output line, and signal line 30 is a synchronization result input line.

The computer 11 includes an arithmetic processing unit 20 that performs data processing / arithmetic.
A register 21 for holding a synchronization pattern, a matching circuit 22 for detecting a synchronization state, and an output line 2 of the register 21.
Switching circuit 23 for selecting 11 and the synchronizing signal input line 27
A switching circuit 24 for selecting the synchronization result input line 30 and the synchronization signal input line 27, and a holding circuit 25 for holding the states of the switching circuits 23, 24. Calculator 1, 12,
13, 111, 112, 113 also have the same configuration as the computer 11.

First, the synchronization of only one stage of the computers 11, 12, and 13 will be described.

Prior to the synchronization processing, in the computer 1, the synchronization bus circuit 26
The internal circuit corresponding to the synchronizing signal switching circuits 23 and 24 in the computer 11 is switched so that the output of the above is connected to the synchronizing result input line 30. When the next synchronization becomes necessary, in the computer 11, the synchronization pattern indicating the type of synchronization from the arithmetic processing unit 20 is written in the register 21, and this synchronization pattern is transmitted through the synchronization signal switching circuit 23 to the synchronization signal output line 2
9 and is input to the synchronization signal bus circuit 26. Similarly, the sync signal patterns from the computers 12 and 13 are also input to the sync signal bus circuit 26. These sync signal patterns are wired and logic by the sync bus circuit 26,
It is transmitted to the synchronization result input line 30 via the computer 1. In the computer 11, the coincidence circuit 22 compares the transmitted result with the synchronization pattern written in the register 21, and when they coincide, the coincidence result is transmitted to the arithmetic processing unit 20. The series of operations similarly occurs for the computers 12, 13 and the computers 11, 12, 13 are synchronized.

Similarly, by switching the synchronization signal switching circuit 24 in the computer 11 so that the signal of the synchronization signal input line 27 is transmitted to the synchronization result output line 28, the computers 111, 112, 11
The synchronization of 3 is also realized.

Next, the computer 1 and the computers 11, 12, 13 and the computer 11
The synchronization over three stages of 1, 112, 113 will be described.

In this case, in the computer 11, the sync signal switching circuit 23 is switched so that the sync signal of the sync signal input line 27 is transmitted to the sync signal output line 29, and the sync result input line 30 sends the sync result to the sync result output line 28. The synchronization signal switching circuit 24 is switched so as to be transmitted. In the computer 1, the output of the synchronization signal bus circuit 26 is switched so as to be transmitted to the synchronization result input line 30.

When the next synchronization is required, the computer 11 writes the synchronization pattern indicating the type of synchronization from the arithmetic processing unit 20 into the register 21, but the synchronization pattern is not transmitted to the synchronization signal output line 29. Other computer 1 and computer 12, 1
3 and the computers 111, 112 and 113 perform similar operations. On the other hand, for the computers 111, 112, 113, after the output of the synchronization signal from each computer is transmitted through the synchronization signal bus circuit 261, the wiring and logic is taken,
It is transmitted to the synchronization signal input line 27 of the computer 11, further transmitted to the synchronization signal output line 29, the synchronization result input line 30, the synchronization result output line 28, and finally to the computers 111, 112,
The result of synchronization is transmitted to 113.

In the computer 11, the result of the synchronization result input line 30 and the synchronization pattern written in the register 21 match the circuit 2.
2 is compared, and if they match, the matching result is transmitted to the arithmetic processing unit 20. This operation similarly occurs for the other computers 1, the computers 12, 13, and the computers 111, 112, 113. That is, the synchronization is realized in all of the computers 1, 11, 12, 13 and the computers 111, 112, 113 which are connected in multiple stages and propagate the synchronization result.

In FIG. 1, a register 21, a matching circuit 22, synchronous switching circuits 23 and 24, a synchronous signal input line 27, a synchronous signal output line 29, a synchronous signal input line 30, a synchronous signal output line 28, and synchronous signal bus circuits 26 and 261. Can be composed of a plurality of bits and a plurality of signal lines, and it can be easily inferred that some of these are switched for one-stage synchronization designation and some of them are switched for multi-stage synchronization designation. Further, if it is assumed that there is one computer at each stage in FIG. 1, it can be easily inferred that the synchronization of the configuration in which a plurality of computers are connected in a ring can be realized as it is.

The switching state holding circuit 25 is a mechanism for holding the states of the synchronization signal switching circuits 23 and 24 in accordance with the switching designation from the arithmetic processing unit 20, and the arithmetic processing unit 20 knows the states of the switching circuits 23 and 24. Use in case.

FIG. 2 is a diagram showing another embodiment of the present invention, in which the built-in synchronizing signal bus circuit 231 for the synchronizing signal input line 27 and the register output 211 is provided on the input side of the synchronizing signal switching circuit 23 in the computer 11. Is connected. In FIG. 2, the synchronizing signal input line 27 and the register output line 211 are shown.
By laying out the wiring logic with, the synchronization designating more synchronization patterns than the embodiment of FIG. 1 is realized.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, in a composite computer system in which a plurality of computers are connected in a multi-stage or annular manner, each computer is notified of a register holding a synchronization pattern and the synchronization pattern to the next stage. By providing a switching circuit for selecting whether to switch or not, it is possible to realize synchronization between arbitrary stages and multi-pattern synchronization at high speed. Therefore, for example, an efficient synchronization method can be provided in applications such as load distribution processing by allocating data to multi-stage connected multi-function computer systems, image generation processing for parallel independent processing, dictionary search, and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, FIG. 3 is a diagram showing an example of a multi-stage connection-type composite computer system, and FIG. It is a figure which shows an example of the multi-functional computer system of a ring connection structure. 1 ... Top-stage computer, 11, 12, 13 ... Second-stage computer, 111, 112, 113 ... Third-stage computer, 20 ...
... arithmetic processing unit, 21 ... register, 22 ... matching circuit,
23, 24 ... Synchronous signal switching circuit, 25 ... Switching state holding circuit, 26, 261, ... Synchronous signal bus circuit, 27 ...
Sync signal input line, 28 ... Sync result output line, 29 ... Sync signal output line, 30 ... Sync result input line.

Claims (1)

[Claims] 1. In a composite computer system in which a plurality of computers are connected in a plurality of stages or in a ring, a register holding a synchronization pattern and a synchronization pattern of the register are propagated to the next stage or to the previous stage in each computer. A switching circuit that selects whether to pass the synchronization pattern transmitted from the next stage to the next stage, and propagates the synchronization result returned from the next stage to the previous stage, or returns the synchronization pattern transmitted from the previous stage to the previous stage. And a switching circuit to select
A matching circuit for determining whether the synchronization pattern held in the register and the synchronization result returned from the next stage are matched is provided, both switching circuits are set in a predetermined combination, and the synchronization pattern is sent to the register. After setting, the matching circuit determines whether the synchronization result sent back from the next stage matches the synchronization pattern held in the register. A computer-to-computer synchronization method characterized by: