JPH03214334A - Fault information collecting system - Google Patents

Abstract

PURPOSE:To execute the collection of fault information by reducing the processing of a service processor by transferring the data stored in a storage device to the service processor after all the fault information is stored in the storage device. CONSTITUTION:Whenever a scan loop 100 is allowed to step by a prescribed number, an address counter 102 is allowed to step, and scan information allowed to step by a prescribed number is stored in a storage area of a storage device 101 of an address shown by the address counter 102. Thereafter, the system is constituted so that data stored in the storage device 101 is transferred to a service processor 103. Accordingly, the data transfer of the service processor 103 can transfer continuously the data, and a high speed transfer can be executed. In such a way, when a fault occurs, the time when the service processor 103 is restricted by the collection processing of fault information is shortened.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to collect fault information by reducing the processing of the service processor, regarding an information processing system having at least a service processor and a processing device having a scan lube for storing fault information. and a scan loop composed of a plurality of registers for storing failure information, a storage device for storing data of the scan loop, and an address counter for giving an address of a data storage destination to the storage device, Every time the loop is incremented by a predetermined number of steps, the address counter is incremented, and the scan information incremented by the predetermined number of steps is stored in the storage area of the storage device at the address indicated by the address counter, and all fault information is stored. The configuration is such that the data stored in the storage device is transferred to the service processor after being stored in the storage device.

[Industrial application field]

The present invention relates to a process for collecting fault information in a computer system.

In recent years, computer systems have come to be composed of a large number of processing devices that integrate large-scale circuits, so it has become difficult to collect fault information when a fault occurs.

For example, if a hardware failure occurs in one processing unit and the failure spreads to multiple processing units, SVP (SerVice Processor
: A processing device that manages each processing device in a computer system) must collect fault information for all the processing devices in which a fault has occurred. For this reason, the time required by the svp to collect failure information becomes enormous.

In general, the svp performs many other processes in addition to collecting fault information, so if the collecting process of fault information takes a long time, the performance of the entire computer system will be degraded as a result.

[Conventional technology]

Figure 4 is an explanatory diagram of conventional technology in computer systems. 1-1 is the SYSTEM that connects each processing device
bus, 1-2 are SvP interfaces used by svp to control each processing device. ■-3 is CPIJ (C
internal processing unit),
1-4 is MAC (Me+wory8ccess
Controller), 1-5 are MSU(M
memory StorageUnit), l-(i
, l-7 is Cfl (Clannel), 1-8
indicates SvP (SerVice Processor). As shown in the figure, each processing device has a SYS
An SvP interface is connected separately from the TEM bus. FIG. 5 is an explanatory diagram of the conventional technology in each processing device. Among the processing devices shown in FIG. 4, svp
All other processing devices have a configuration as shown in FIG. 2-1 is a normal circuit that realizes the unique functions of each processing device;
2-2 is an svp interface circuit that communicates with SvP, and 2-3 is a SYSTEM that connects each processing device.
bus (signal &9 shown as 1-1 in Figure 4),
2-4 is the SvP interface (signal line shown as 1-2 in FIG. 4) which is a signal line with SvP, 25 is an FF (Flip Flop) that constitutes a normal circuit, and 2-6 is an SvP interface
A control circuit 2-7 for controlling the vP interface is a scan register used for loop scanning of a normal circuit. In addition, the 2-4 SVP interface provides Scan In and Scan Out for collecting scan data.
t, Scan Clo for performing loop scan
ckA, Scan Clock B, 11^LT indicating that a failure has occurred in the processing device and entered the It A l, T state, Reset to reset the processing device
It consists of signals such as When a failure occurs in a processing device other than svp in a computer system, that processing device
It becomes LT state.

The fact that the processing device has entered the IIALT state means that SvP
SvP is notified by the IIALT signal of the interface.

When svp detects IIALT of the processing device, Scan
Two signal lines, Clock^ and Scan Clock B, are used to shift the scan loop of the normal circuit, and Scan In and Scan O are also used to shift the scan loop of the normal circuit.
The contents of the scan register are scanned using the ut signal line, and the values of the FFs on the normal circuit are read. The read FFO value is recorded and analyzed by SvP as fault information.

An example of operation will be explained according to FIG.

When the control circuit detects HALT of the device, the control circuit switches to normal circuit 2.
-1 basic clock is stopped. It also notifies the service processor that it is HALT. When the service processor recognizes it, the svP interface
From SCAN Cl, OCK A, SCAN CLO
CK B is input to the SvP interface circuit 2-2. This SCAN CLOCK A, SCAN CL
OCK B is FF 2-5 and scan register 2-
The reason why two clocks are inputted to operate 7 is because it is composed of a master-slave latch.

First, the control circuit 2-6 sends 8 clocks to the FFs 2-5 and increments OFF by 8 bits each. The scan information incremented by 8 bits is stored in the scan register 27. Then, SvP takes in the scan register 2-7 through SCAN OtlTL, and svp takes in the fault information.

At this time, FF 2-5 does not step.

That is, ■ 8-bit increments of FFs 2-5. ■SvP scans out the data in scan registers 2-7. All data of FF 2-5 is SvP
Continue until transferred to .

[Problem to be solved by the invention]

Each processing device that constitutes a computer system consists of a large number of integrated circuits. As the amount of integrated circuits is increasing year by year,
The number of FFs to be collected by scanning when a failure occurs has also increased. In addition, the number of processing devices that make up a computer system increases, and one processing device may fail due to a failure.
In some cases, multiple devices were forced to HALT due to ripple effects.

For these reasons, the time required for SVP failure information collection processing has increased, and other processing that SvP should perform has come to be interrupted for a long time in some cases.

For example, when a failure occurs in a certain processing device in a computer system, it may take several minutes to complete the collection of failure information. Therefore, if the CPU executes an instruction that requests processing to the svp while failure information is being collected, the processing related to that instruction may be interrupted for several minutes.

[Means to solve problems]

FIG. 1 is a diagram showing the principle of the present invention.

A processing device (with a scan loop that stores failure information)
In an information processing system having at least a service processor (101), a scan loop (10
0), a storage device (101) for storing data of the scan loop, and an address counter (102) for giving an address of a data storage destination to the storage device, the scan loop (100) Every time you advance,
The address counter (102) is incremented, and the scan information incremented by the predetermined number is transferred to the address counter (102).
2), and after all fault information is stored in the storage device (101), the data stored in the storage device (101) is stored in the storage area of the address storage device (101). (103).

[Effect]

Each time the scan loop is incremented by a predetermined number of steps, the address counter is incremented, and the scan information that has been incremented by the predetermined number of steps is stored in a storage area number of the storage device at the address indicated by the address counter.

After that, the configuration is such that the data stored in the storage device is transferred to the service processor. In other words, in the conventional example, data is transferred every time it is stored in the scan register, but in the present invention, data is transferred after all fault information is stored in the storage device, so data is transferred continuously by the service processor. The normal circuit that can be transferred to the device realizes its own functions,
3-2 is an SvP interface circuit that communicates with SVP, and 33 is a SYSTEM that connects each processing device.
bus, 3-4 is the SvP interface which is a signal line with SVP, and 3-5 is L for transferring fault information at high speed.
OGGING bus, 3-6 is the F that constitutes the normal circuit.
F (Flip Flop), 3-7 is a control circuit that controls the SvP interface, 3-8 is a scan register used for loop scanning of a normal circuit, 3-9 is a RAM that temporarily stores fault information obtained by scanning, 3-10
is an address counter that generates an address on the RAM when storing failure information in the RAM. Also, 3-4 S
The VP interface is disabled due to a processing unit failure.
It consists of signals such as HALT indicating that the LT state has been entered, LOGGINGEND indicating the end of failure collection processing, and Reset for resetting the processing device. Also,
3-5 LOGGING bus is ScanDATA, Sca used to transfer fault information from RAM.
It consists of signals such as n Address. Also, 3-
2. Since the SVP interface circuit is configured independently from the 3-1 normal circuit, the 3-1 normal circuit is HALT L.
It is possible to operate even if the

When a fault occurs in the normal circuit and HALT occurs, the SvP interface circuit turns on the }IALT signal of the SvP interface and notifies the svp that the processing device is HALT. At the same time, the normal circuit is scanned and the RAM
Store failure information in When all FFs have been scanned and failure information has been collected, the svp ink face L
Turns on the OGGING END signal and notifies the svp of the completion of failure information collection.

When the svp receives the failure information collection completion notification, it quickly collects the failure information using the LOGGING bus of the svp interface.

Even if the svp receives a HALT notification from a processing device, it is not necessary to collect failure information through scanning, and it is sufficient to simply recognize the HALT of the processing device.

The SvP interface circuit independently performs the time-consuming process of sending a cross to the normal circuit, shifting data on the scan loop, and collecting fault information. When the collection of failure information is completed, the SvP interface circuit notifies this using the scan LOGGINGEND signal, so that SvP can perform other processing until this notification is received.

When the completion of failure information collection is reported by the LOGGING END signal, svp sends LOGG for failure information transfer.
Fault information is transferred using INGbus. This transfer can be performed as fast as the access performance of the RAM in the SvP interface circuit allows.

An example of operation will be explained according to FIG.

When the control circuit detects HALT of the device, the normal circuit 3
-1 basic clock is stopped. It also notifies the service processor that it is HALT. First, control circuit 3
-7 is FF 8 clocks are sent to 3-6 (7) F
Increments F by 8 bits. The scan information incremented by 8 bits is stored in the scan register 3-8. After storing, l? of the address specified by address counter 3-10? The scan data in the scan register 3-8 is stored in AM 3-9. That is, every time the FF 36 increments by 8 bits, the address counter 31O is added and the address is written to the RAM 3-9.
F Repeat until all scan data of 3-6 is stored.

When all the data is stored in the RAM 3-9, the control circuit 3-7 sends a LOGGING END signal from the svp ink 7 ace 3-4 to the SvP to notify that logging has ended. And svp is LOGGING
The log information of the RAM 3-9 is read via Bus 3-5.

Scan DATA Address bus is 3-
5 3-9 RAM using LOGGING bus
This is for the SvP to specify in lbbyte units which address in the 3-9 RAM is to be transferred data when transferring data from the 3-9 RAM to the svp. In other words, 3-
5 LOGGING bus Scan DATAAd
The dress bus is a signal that is not input to the 3-10 address counter, but is input to the 3-9 RAM.

The value of the 3-10 address counter becomes the initial value "0" address by the reset signal of the 3-4 SVP interface.

FIG. 3 shows an embodiment of the present invention in a computer system. 4-1 is the SYSTEM bus that connects each processing device
, 4-2 is an SvP interface used by svp to control each processing device, and 4-3 is a LOGGING bus for transferring failure information from each processing device to svp.
, 4-4 is CPLI (Central Proc
essing Unit), 4-5 are MAC (Memo
ry Access Controller), 4-6 is MS port (Memory Storage Unit)
, 4-'L4-8 is CH (CHannel) 4-9 is S
VP (Ser Vice Processor) is shown. As shown in the figure, each processing unit has a SYSTE
svp interface and LOG separately from M bus
GING bus is connected. FIG. 2 applies to the contents of each processing device other than svp.

〔Effect of the invention〕

As explained above, according to the present invention, when a failure occurs, s
It is possible to significantly reduce the time that the VP is bound to collect failure information. Further, the present invention can be realized with a relatively simple circuit as shown in FIG.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIGS. 2 and 3 are embodiments of the present invention, and FIGS. 4 and 5 are conventional techniques. 100 ----- Scan loop 101 --- Storage device 102 ----- Address counter 103 --
-----SVP

Claims (1)

[Claims] A processing device (
In an information processing system having at least a service processor (101) and a service processor (101), a scan loop (10
0), and a storage device (10) for storing data of the scan loop.
1); an address counter (102) for giving an address of a data storage destination to the storage device; and each time the scan loop (100) is incremented by a predetermined number of steps, the address counter (102) is incremented; The scan information incremented by a predetermined number of steps is sent to the address counter (1
02) in the storage area of the storage device (101), and after all fault information is stored in the storage device (101), the data stored in the storage device (101) is stored in the service processor (103). ) is a fault information collection method characterized by forwarding to