JPS62174839A - Recognition system for normalcy of subsystem in duplex system - Google Patents
Recognition system for normalcy of subsystem in duplex systemInfo
- Publication number
- JPS62174839A JPS62174839A JP61017129A JP1712986A JPS62174839A JP S62174839 A JPS62174839 A JP S62174839A JP 61017129 A JP61017129 A JP 61017129A JP 1712986 A JP1712986 A JP 1712986A JP S62174839 A JPS62174839 A JP S62174839A
- Authority
- JP
- Japan
- Prior art keywords
- sby
- processor
- act
- control processor
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims abstract description 13
- 230000004913 activation Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 238000012790 confirmation Methods 0.000 claims 2
- 238000003745 diagnosis Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
Landscapes
- Small-Scale Networks (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は二重化構成の分散処理型データ交換機に関し、
特に予備系の正常性確認方式に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a distributed processing data exchanger with a redundant configuration,
In particular, it relates to a method for confirming the normality of a standby system.
従来この種のデ・−夕交換機は第２図に示す様に、制御
プロセッサと処理プロセッサは同一方式によって構成さ
れていた。Conventionally, this type of data exchange has had a control processor and a processing processor constructed using the same system, as shown in FIG.
２−１は二重化された制御プロセッサで、２−２は複数
ある二重化された処理モジュールの内の１つを示してい
る。２−３はバス制御回路でプロセッサ間の情報伝送を
行う。２−４は制御プロセッサ２−５や処理プロセッサ
２−６１２−６ｌの間のインタフェース回路で２−７の
切替回路により、接続相手を切替えられる。2-1 is a duplicated control processor, and 2-2 is one of a plurality of duplicated processing modules. 2-3 is a bus control circuit that transmits information between processors. Reference numeral 2-4 is an interface circuit between the control processor 2-5 and the processing processors 2-612-6l, and the connection partner can be switched by a switching circuit 2-7.
この様なシステムに於いて、 ＳＢＹの制御プロセッサ
ーはＳＢＹの処理プロセッサの正常性確認全周期的に行
い、プロセッサ間インタフェース２−８を介して、ＡＣ
Ｔ制御プロセッサに報告していた。In such a system, the SBY control processor periodically checks the normality of the SBY processor, and controls the AC
It was reporting to the T control processor.
上述した従来の制御プロセッサの構成では、ＡＣＴの制
御プロセッサはＳＢＹの処理プロセッサ群の状態１ＳＢ
Ｙの制御プロセッサを介して、間接的にしか知ることが
出来ず、ＳＢＹの制御プロセッサ障害時、保守者が駆け
つけ障害復旧するまで、ＳＢＹ系の状態は全く知ること
が出来なくなってしまう。In the conventional control processor configuration described above, the ACT control processor is in the state 1SB of the SBY processor group.
It can only be known indirectly through the control processor of Y, and when a failure occurs in the control processor of SBY, the status of the SBY system cannot be known at all until a maintenance person rushes in and recovers from the failure.
又、ＳＢＹの制御プロセッサは、ＳＢＹの処理プロセッ
サ処理のためのプログラムを走らせているため、ＡＣＴ
になった時に必要な、ハードウェア全体の正常性を完全
に行うことは困難であるという問題点があった。In addition, since the SBY control processor runs a program for SBY processing processor processing, the ACT
There was a problem in that it was difficult to completely check the health of the entire hardware, which is necessary when
本発明はＡＣＴの制御プロセッサは、ＳＢＹの処理プロ
セッサ群の正常性の確認？行うために。In the present invention, does the ACT control processor confirm the normality of the SBY processing processor group? To do.
両方の通信バスに接続される機構と、ＳＢＹの制御プロ
セッサは両方の通信バスから切離される機構及びＳＢＹ
の制御プロセッサは、ＡＣＴ制御プロセッサよシ診断起
動全受け、又１診断結果を報告するプロセッサ間インタ
フェースを有する。A mechanism that is connected to both communication buses and a control processor of SBY is a mechanism that is disconnected from both communication buses and SBY.
The control processor has an inter-processor interface for receiving all diagnostic activation from the ACT control processor and for reporting diagnostic results.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。１
−１はシステムに１つ存在する二重化構成の制御プロセ
ッサで、１−２は１−２の複数ある二重化された処理モ
ジュールの内の１つを示しておシ、内部の説明は第２図
と同じであシここで省略する。１−３（ＡＪはＡＣＴの
通信バス制御回路、１−３ （８１はＳＢＹの通信バス
制御回路でプロセッサ間の情報伝送を行う。ｌ−４（５
）は八〇Ｔの制御プロセッサ、１−４（Ｓ）はＳＨＹの
制御プロセッサでそれぞれ２組の１−３とのインタフェ
ース回路１−５ｆｔ備えておシ、１−４（Ａｌは接続切
替え回路１−６により両方の１−３に接続され、１−４
（Ｂｌは切離される様に動作する。１−４因はＡＣＴ系
システムの運用全行うと同時に、ＳＢＹ系の処理プロセ
ッサ群の正常性確認上行い、更にプロセッサ間インタフ
ェース１−７を介して、１−４＋８１に対して診断コマ
ノド全発行し、父上の応答全党けて正常性のＳＢＹの制
御プロセッサーの正常性全ｇ認する。FIG. 1 is a block diagram showing one embodiment of the present invention. 1
-1 is a control processor with a duplex configuration that exists in the system, and 1-2 indicates one of the multiple duplex processing modules 1-2.The internal explanation is as shown in Figure 2. It's the same, so I'll omit it here. 1-3 (AJ is the communication bus control circuit of ACT, 1-3 (81 is the communication bus control circuit of SBY, which transmits information between processors. l-4 (5
) is an 80T control processor, 1-4 (S) is a SHY control processor, and each has a 1-5ft interface circuit with two sets of 1-3. -6 connects to both 1-3, 1-4
(Bl operates as if it were disconnected. The reason for 1-4 is to confirm the normality of the SBY system processor group at the same time as performing all operations of the ACT system, and furthermore, via the inter-processor interface 1-7, All diagnostic commands were issued to 1-4+81, and all of the father's responses confirmed the normality of SBY's control processor.
以上説明した様に本発明はＡＣＴの制御プロセッサがＳ
ＢＹの処理プロセッサ群とＳＢＹの制御プロセッサの正
常性２を確認する機能金持たせた事によ、９、ＳＢＹの
制御プロセッサ障害でもＳＢＹの処理プロセッサの状態
監視が行え、又、ＳＢＹの制御プロセッサの詳細診断が
行えるため、８８Ｙの制御プロセッサ全体のハードウェ
アの監視が行える効果がある。As explained above, in the present invention, the ACT control processor
By having a function to check the normality of the BY processing processor group and the SBY control processor, it is possible to monitor the status of the SBY processing processor even in the event of a SBY control processor failure. Since detailed diagnosis can be performed, the hardware of the entire 88Y control processor can be monitored.
第１図は本発明の一実施例を示すブロック図、第２図は
従来例を示すブロック図である。
１−１・・・・・・二重化構成のシステム制御プロセッ
サ、１−２・・・・・・二重化構成の処理プロセッサ、
１−３・・・・・・通信バス制御回路、１−４・・・・
・・制御プロセッサ、１−５・・・・・・通信バスープ
ロセッサ間インタフェース、１−６・・・・・・接続切
替え回路、１−７・・・・・・プロセッサ間インタフェ
ース。
２．７Ｓ。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1-1... System control processor with duplex configuration, 1-2... Processing processor with duplex configuration,
1-3... Communication bus control circuit, 1-4...
Control processor, 1-5 Communication bus-processor interface, 1-6 Connection switching circuit, 1-7 Inter-processor interface. 2.7S.
Claims (1)
た制御プロセッサとシステムに複数存在し、データ交換
処理を行う二重化された処理プロセッサを二本のプロセ
ッサ間通信バス（以下通信バス）で片側のプロセッサづ
つを接続する、二重化構成の分散処理型データ交換機に
於いて、制御プロセッサの現用側（以下ＡＣＴ）は両方
の通信バスに結合される手段と、予備側（以下ＳＢＹ）
は通信バスから完全に切離される手段及び制御プロセッ
サのＡＣＴとＳＢＹ間にコマンド起動及び応答情報の授
受を行う手段を有し、ＡＣＴの制御プロセッサはＡＣＴ
の通信バス及び処理プロセッサを使ってデータ交換処理
を行うと共に、ＳＢＹの通信バスを介してＳＢＹの処理
プロセッサに周期的に正常性確認コマンドを発行し、そ
の応答を受けることにより、ＳＢＹの処理プロセッサの
状態を常時監視し、更にＳＢＹの処理プロセッサはＡＣ
Ｔの制御プロセッサがＳＢＹの処理プロセッサの状態監
視を行ってくれることから何もしなくて良く、ＡＣＴの
制御プロセッサの指示により内蔵している詳細診断プロ
グラムを走らせ、ハードウェアの正常性を確認して応答
をＡＣＴの制御プロセッサに返すことを常時行うことに
より、ＡＣＴ系のみならず、ＳＢＹ系の状態を確実に把
握することを特徴とする予備系の正常性確認方式。One system exists, with a redundant control processor that controls the system, and a system with multiple redundant processing processors that perform data exchange processing. In a dual-configured distributed processing data exchange that connects two communication buses, the active side (hereinafter referred to as ACT) of the control processor has a means to be connected to both communication buses, and the standby side (hereinafter referred to as SBY).
has means to be completely separated from the communication bus and means to send and receive command activation and response information between the control processors ACT and SBY, and the control processor of the ACT is connected to the ACT.
In addition to performing data exchange processing using the communication bus and processing processor of SBY, periodically issuing a normality confirmation command to the processing processor of SBY via the communication bus of SBY, and receiving the response, the processing processor of SBY The status of SBY is constantly monitored, and SBY's processor is
Since T's control processor monitors the status of SBY's processing processor, there is no need to do anything, and the built-in detailed diagnostic program is run according to instructions from ACT's control processor to check the health of the hardware. A standby system normality confirmation method characterized in that the status of not only the ACT system but also the SBY system can be reliably grasped by constantly returning responses to the ACT control processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61017129A JPS62174839A (en) | 1986-01-28 | 1986-01-28 | Recognition system for normalcy of subsystem in duplex system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61017129A JPS62174839A (en) | 1986-01-28 | 1986-01-28 | Recognition system for normalcy of subsystem in duplex system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62174839A true JPS62174839A (en) | 1987-07-31 |
Family
ID=11935422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61017129A Pending JPS62174839A (en) | 1986-01-28 | 1986-01-28 | Recognition system for normalcy of subsystem in duplex system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62174839A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6462048A (en) * | 1987-09-01 | 1989-03-08 | Fuji Electric Co Ltd | Duplex system for data transmitter |
| JP2011022741A (en) * | 2009-07-15 | 2011-02-03 | Nec Computertechno Ltd | Computer system, service processor, and diagnostic method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155649A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Centralized controlling system |
| JPS57155648A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Diagnosing system of stand-by group information processor |
-
1986
- 1986-01-28 JP JP61017129A patent/JPS62174839A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155649A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Centralized controlling system |
| JPS57155648A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Diagnosing system of stand-by group information processor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6462048A (en) * | 1987-09-01 | 1989-03-08 | Fuji Electric Co Ltd | Duplex system for data transmitter |
| JP2011022741A (en) * | 2009-07-15 | 2011-02-03 | Nec Computertechno Ltd | Computer system, service processor, and diagnostic method thereof |
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