JPS6188243U - - Google Patents

Info

Publication number
JPS6188243U
JPS6188243U JP1984172862U JP17286284U JPS6188243U JP S6188243 U JPS6188243 U JP S6188243U JP 1984172862 U JP1984172862 U JP 1984172862U JP 17286284 U JP17286284 U JP 17286284U JP S6188243 U JPS6188243 U JP S6188243U
Authority
JP
Japan
Prior art keywords
metal layer
laminated metal
electrode
bump electrode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984172862U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984172862U priority Critical patent/JPS6188243U/ja
Publication of JPS6188243U publication Critical patent/JPS6188243U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例による半導体装置の
バンプ電極製作工程を順次示す断面図、第2図は
従来のバンプ電極製作工程の一部を示す断面図、
第3図は本考案の一実施例におけるバンプ電極と
隆起部との関係位置を示す平面図ずある。 1:シリコン基板、2,11:酸化シリコン膜
、3:Al電極層、4:保護膜、5:密着金属層
、6:バリヤ金属層、7:フオトレジスト、8:
バンプ電極、10:隆起部、12:環状酸化膜。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板の電極層上に積層金属層を介してバ
    ンプ電極が設けられるものにおいて、積層金属層
    の最表面がバンプ電極の下面に接近して包囲する
    隆起部を有することを特徴とする半導体装置。
JP1984172862U 1984-11-14 1984-11-14 Pending JPS6188243U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984172862U JPS6188243U (ja) 1984-11-14 1984-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984172862U JPS6188243U (ja) 1984-11-14 1984-11-14

Publications (1)

Publication Number Publication Date
JPS6188243U true JPS6188243U (ja) 1986-06-09

Family

ID=30730521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984172862U Pending JPS6188243U (ja) 1984-11-14 1984-11-14

Country Status (1)

Country Link
JP (1) JPS6188243U (ja)

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