JPH0254235U - - Google Patents
Info
- Publication number
- JPH0254235U JPH0254235U JP1988134075U JP13407588U JPH0254235U JP H0254235 U JPH0254235 U JP H0254235U JP 1988134075 U JP1988134075 U JP 1988134075U JP 13407588 U JP13407588 U JP 13407588U JP H0254235 U JPH0254235 U JP H0254235U
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- insulating film
- interlayer insulating
- opening
- layer provided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 6
- 239000002184 metal Substances 0.000 claims 6
- 239000011229 interlayer Substances 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図ａ，ｂは本考案の第１の実施例を説明す
るための半導体チツプの平面図及びＡ―Ａ′線断
面図、第２図ａ，ｂは本考案の第２の実施例を説
明するための半導体チツプの平面図及びＢ―Ｂ′
線断面図、第３図ａ，ｂは従来の半導体装置を説
明するための半導体チツプの平面図及びＣ―Ｃ′
線断面図である。 １……半導体基板、２……絶縁膜、３……チタ
ン層、４……酸化シリコン膜、５……開孔部、６
……タングステン層、７……アルミニウム層、８
……ＰＳＧ膜、９……開孔部。
るための半導体チツプの平面図及びＡ―Ａ′線断
面図、第２図ａ，ｂは本考案の第２の実施例を説
明するための半導体チツプの平面図及びＢ―Ｂ′
線断面図、第３図ａ，ｂは従来の半導体装置を説
明するための半導体チツプの平面図及びＣ―Ｃ′
線断面図である。 １……半導体基板、２……絶縁膜、３……チタ
ン層、４……酸化シリコン膜、５……開孔部、６
……タングステン層、７……アルミニウム層、８
……ＰＳＧ膜、９……開孔部。
Claims (1)
- 半導体基板上に設けた絶縁膜上に設けた第１の
金属層と、前記第１の金属層を含む表面に設けた
層間絶縁膜と、前記第１の金属層上の前記層間絶
縁膜に設けた開孔部と、前記開孔部を含む前記層
間絶縁膜上に設けて前記開孔部の前記第１の金属
層と接続する第２及び第３の積層された金属層か
らなる電極パツドとを有することを特徴とする半
導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134075U JPH0254235U (ja) | 1988-10-13 | 1988-10-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134075U JPH0254235U (ja) | 1988-10-13 | 1988-10-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0254235U true JPH0254235U (ja) | 1990-04-19 |
Family
ID=31392499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988134075U Pending JPH0254235U (ja) | 1988-10-13 | 1988-10-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0254235U (ja) |
-
1988
- 1988-10-13 JP JP1988134075U patent/JPH0254235U/ja active Pending