JPH0395635U - - Google Patents

Info

Publication number
JPH0395635U
JPH0395635U JP1990001721U JP172190U JPH0395635U JP H0395635 U JPH0395635 U JP H0395635U JP 1990001721 U JP1990001721 U JP 1990001721U JP 172190 U JP172190 U JP 172190U JP H0395635 U JPH0395635 U JP H0395635U
Authority
JP
Japan
Prior art keywords
groove
insulating film
circuit
wiring
embedding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990001721U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990001721U priority Critical patent/JPH0395635U/ja
Publication of JPH0395635U publication Critical patent/JPH0395635U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】
第1図a,bは本考案の第1の実施例の平面図
及びA−A′線断面図、第2図a,bは本考案の
第2の実施例の平面図及びB−B′線断面拡大図
である。 1……シリコン基板、2……パツド電極、3…
…開孔部、4……配線引出し部、6……パツシベ
ーシヨン酸化膜、7……フイールド酸化膜、8…
…溝、9……窒化シリコン膜、10……アルミニ
ウム配線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板上に設けた絶縁膜と、前記絶縁膜の
    表面に設けた溝と、前記溝内に金属膜の一部を埋
    込んで設けた配線又はパツド電極を備えたことを
    特徴とする半導体集積回路。
JP1990001721U 1990-01-12 1990-01-12 Pending JPH0395635U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990001721U JPH0395635U (ja) 1990-01-12 1990-01-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990001721U JPH0395635U (ja) 1990-01-12 1990-01-12

Publications (1)

Publication Number Publication Date
JPH0395635U true JPH0395635U (ja) 1991-09-30

Family

ID=31505615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990001721U Pending JPH0395635U (ja) 1990-01-12 1990-01-12

Country Status (1)

Country Link
JP (1) JPH0395635U (ja)

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