JPH03102729U - - Google Patents
Info
- Publication number
- JPH03102729U JPH03102729U JP1057890U JP1057890U JPH03102729U JP H03102729 U JPH03102729 U JP H03102729U JP 1057890 U JP1057890 U JP 1057890U JP 1057890 U JP1057890 U JP 1057890U JP H03102729 U JPH03102729 U JP H03102729U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- metal wiring
- outer periphery
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000000605 extraction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案によるチツプの平面図、第２図
は従来のチツプの平面図である。 １……ＩＣチツプ、２……電極取出しパツド、
３……周囲電極配線、４……ＩＣチツプ端部。
は従来のチツプの平面図である。 １……ＩＣチツプ、２……電極取出しパツド、
３……周囲電極配線、４……ＩＣチツプ端部。
Claims (1)
- 半導体装置のチツプにおいて、該チツプ表面上
の周囲のエツジより所定間隔をとつた内側に該エ
ツジの外周に添つて、金属配線を設けかつ、当該
金属配線は該チツプの素子分離領域を介して下部
のサブストレートに接続された半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057890U JPH03102729U (ja) | 1990-02-07 | 1990-02-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057890U JPH03102729U (ja) | 1990-02-07 | 1990-02-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03102729U true JPH03102729U (ja) | 1991-10-25 |
Family
ID=31514137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1057890U Pending JPH03102729U (ja) | 1990-02-07 | 1990-02-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03102729U (ja) |
-
1990
- 1990-02-07 JP JP1057890U patent/JPH03102729U/ja active Pending