JPS6268236U - - Google Patents
Info
- Publication number
- JPS6268236U JPS6268236U JP1985158644U JP15864485U JPS6268236U JP S6268236 U JPS6268236 U JP S6268236U JP 1985158644 U JP1985158644 U JP 1985158644U JP 15864485 U JP15864485 U JP 15864485U JP S6268236 U JPS6268236 U JP S6268236U
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- integrated circuit
- semiconductor integrated
- circuit device
- lower wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図ａ，ｂは本考案の一実施例における識別
を附したボンデイングパツドの平面図及びそのＡ
Ａ線断面図、第２図ａ，ｂは従来構造及び識別を
行わないボンデイングパツドの平面図及びそのＡ
Ａ線断面図である。 １，１１……半導体基板、２，１２……シリコ
ン酸化膜、３，１３……層間絶縁膜としてのシリ
コン酸化膜、４，１４……パツシベーシヨンとし
てのシリコン酸化膜、５，１５……金属配線層、
６，１６……下層配線としての金属配線層、６ａ
……下層パツド、７，１７……スルーホール、７
ａ……識別スルーホール、８，１８……開口。
を附したボンデイングパツドの平面図及びそのＡ
Ａ線断面図、第２図ａ，ｂは従来構造及び識別を
行わないボンデイングパツドの平面図及びそのＡ
Ａ線断面図である。 １，１１……半導体基板、２，１２……シリコ
ン酸化膜、３，１３……層間絶縁膜としてのシリ
コン酸化膜、４，１４……パツシベーシヨンとし
てのシリコン酸化膜、５，１５……金属配線層、
６，１６……下層配線としての金属配線層、６ａ
……下層パツド、７，１７……スルーホール、７
ａ……識別スルーホール、８，１８……開口。
Claims (1)
- 【実用新案登録請求の範囲】 １ 多数個用意されたボンデイングパツドを構成
する品種に応じて任意に選択して使用するマスタ
ースライス方式の半導体集積回路装置において、
使用又は未使用のいずれかのボンデイングパツド
の金属配線層の下側に下層配線層を形成するとと
もに、この下側配線層との間の層間絶縁膜に特異
なパターン形状の識別スルーホールを形成し、ボ
ンデイングパツドの表面側からこの識別スルーホ
ールの特異パターンを認識できるように構成した
ことを特徴とする半導体集積回路装置。 ２ 下層配線層は半導体集積回路装置の回路構成
用の金属配線層の一部で構成してなる実用新案登
録請求の範囲第１項記載の半導体集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985158644U JPS6268236U (ja) | 1985-10-18 | 1985-10-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985158644U JPS6268236U (ja) | 1985-10-18 | 1985-10-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6268236U true JPS6268236U (ja) | 1987-04-28 |
Family
ID=31082328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985158644U Pending JPS6268236U (ja) | 1985-10-18 | 1985-10-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6268236U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04144233A (ja) * | 1990-10-05 | 1992-05-18 | Nec Corp | 半導体集積回路 |
-
1985
- 1985-10-18 JP JP1985158644U patent/JPS6268236U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04144233A (ja) * | 1990-10-05 | 1992-05-18 | Nec Corp | 半導体集積回路 |