JPS633145U - - Google Patents
Info
- Publication number
- JPS633145U JPS633145U JP1986096171U JP9617186U JPS633145U JP S633145 U JPS633145 U JP S633145U JP 1986096171 U JP1986096171 U JP 1986096171U JP 9617186 U JP9617186 U JP 9617186U JP S633145 U JPS633145 U JP S633145U
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- semiconductor
- semiconductor device
- integrated circuit
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000008188 pellet Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例の半導体装置の平面図
、第２図は第１図の断面図、第３図は従来の半導
体装置のペレツトの平面図である。 １，５……ＬＳＩペレツト、２……接続バンプ
、３……配線パターン、４……絶縁フイルム。
、第２図は第１図の断面図、第３図は従来の半導
体装置のペレツトの平面図である。 １，５……ＬＳＩペレツト、２……接続バンプ
、３……配線パターン、４……絶縁フイルム。
Claims (1)
- 一主面上に半導体集積回路素子を有する半導体
基板ペレツトの前記主面の形状が三角形として構
成されることを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986096171U JPS633145U (ja) | 1986-06-23 | 1986-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986096171U JPS633145U (ja) | 1986-06-23 | 1986-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS633145U true JPS633145U (ja) | 1988-01-11 |
Family
ID=30961617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986096171U Pending JPS633145U (ja) | 1986-06-23 | 1986-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633145U (ja) |
-
1986
- 1986-06-23 JP JP1986096171U patent/JPS633145U/ja active Pending