JPH0474426U - - Google Patents
Info
- Publication number
- JPH0474426U JPH0474426U JP1990118148U JP11814890U JPH0474426U JP H0474426 U JPH0474426 U JP H0474426U JP 1990118148 U JP1990118148 U JP 1990118148U JP 11814890 U JP11814890 U JP 11814890U JP H0474426 U JPH0474426 U JP H0474426U
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- padded
- integrated circuit
- circuit device
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の一実施例の要部断面図、第２
図は第１図Ａ部の多結晶シリコンの拡大斜視図、
第３図は従来の半導体集積回路装置の一例の要部
断面図である。 １……半導体基板、２……絶縁膜、３……保護
膜、４……パツドアルミ、５……金属薄膜、６…
…バンプ、７……多結晶シリコン。
図は第１図Ａ部の多結晶シリコンの拡大斜視図、
第３図は従来の半導体集積回路装置の一例の要部
断面図である。 １……半導体基板、２……絶縁膜、３……保護
膜、４……パツドアルミ、５……金属薄膜、６…
…バンプ、７……多結晶シリコン。
Claims (1)
- 半導体基板上に形成された絶縁膜と、該絶縁膜
上に設けられたパツドアルミと、該パツドアルミ
上に金属薄膜を介して形成されたバンプとを有す
る半導体集積回路装置において、前記パツドアル
ミ下に長方体の多結晶シリコンを複数個配置し前
記パツドアルミと前記バンプが前記金属薄膜を介
して凹凸状に接合したことを特徴とする半導体集
積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990118148U JPH0474426U (ja) | 1990-11-09 | 1990-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990118148U JPH0474426U (ja) | 1990-11-09 | 1990-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474426U true JPH0474426U (ja) | 1992-06-30 |
Family
ID=31866055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990118148U Pending JPH0474426U (ja) | 1990-11-09 | 1990-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474426U (ja) |
-
1990
- 1990-11-09 JP JP1990118148U patent/JPH0474426U/ja active Pending