JPH0446542U - - Google Patents

Info

Publication number
JPH0446542U
JPH0446542U JP1990087943U JP8794390U JPH0446542U JP H0446542 U JPH0446542 U JP H0446542U JP 1990087943 U JP1990087943 U JP 1990087943U JP 8794390 U JP8794390 U JP 8794390U JP H0446542 U JPH0446542 U JP H0446542U
Authority
JP
Japan
Prior art keywords
bump
height
semiconductor device
insulating pillow
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990087943U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990087943U priority Critical patent/JPH0446542U/ja
Publication of JPH0446542U publication Critical patent/JPH0446542U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す半導体装置のバ
ンプ形成工程断面図、第２図はその半導体装置の
平面図、第３図は従来の半導体装置におけるＡｕ
バンプ形成工程断面図、第４図は本考案の第２実
施例を示す半導体装置のバンプの平面図、第５図
は本考案の第３実施例を示す半導体装置のバンプ
の平面図、第６図は本考案の第４実施例を示す半
導体装置のバンプの平面図である。 １１……半導体基板、１２，２２，３２，４２
……絶縁性まくら、１３、２３、３３，４３……
電極、１４，２４，３４，４４……パツシベーシ
ヨン膜、１５……バンプ電極。

Claims (1)

  1. 【実用新案登録請求の範囲】 (a) 半導体基板上に絶縁性まくらと、 (b) 該絶縁性まくらを覆うようにして形成され
    た電極から成るバンプと、 (c) 該バンプの周りに形成されるパツシベーシ
    ヨン膜と、 (d) 前記バンプの高さをパツシベーシヨン膜の
    高さより僅かに高く形成することを特徴とする半
    導体装置のバンプ電極構造。
JP1990087943U 1990-08-24 1990-08-24 Pending JPH0446542U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990087943U JPH0446542U (ja) 1990-08-24 1990-08-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990087943U JPH0446542U (ja) 1990-08-24 1990-08-24

Publications (1)

Publication Number Publication Date
JPH0446542U true JPH0446542U (ja) 1992-04-21

Family

ID=31820742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990087943U Pending JPH0446542U (ja) 1990-08-24 1990-08-24

Country Status (1)

Country Link
JP (1) JPH0446542U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303314A (ja) * 2004-04-14 2005-10-27 Samsung Electronics Co Ltd バンプ構造を含む半導体素子及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303314A (ja) * 2004-04-14 2005-10-27 Samsung Electronics Co Ltd バンプ構造を含む半導体素子及びその製造方法

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