JPS6161428B2 - - Google Patents

Info

Publication number
JPS6161428B2
JPS6161428B2 JP55166076A JP16607680A JPS6161428B2 JP S6161428 B2 JPS6161428 B2 JP S6161428B2 JP 55166076 A JP55166076 A JP 55166076A JP 16607680 A JP16607680 A JP 16607680A JP S6161428 B2 JPS6161428 B2 JP S6161428B2
Authority
JP
Japan
Prior art keywords
input
circuit
data
package
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55166076A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5789155A (en
Inventor
Hiroyuki Izumisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55166076A priority Critical patent/JPS5789155A/ja
Publication of JPS5789155A publication Critical patent/JPS5789155A/ja
Publication of JPS6161428B2 publication Critical patent/JPS6161428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP55166076A 1980-11-25 1980-11-25 Integrated logical operation circuit Granted JPS5789155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55166076A JPS5789155A (en) 1980-11-25 1980-11-25 Integrated logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55166076A JPS5789155A (en) 1980-11-25 1980-11-25 Integrated logical operation circuit

Publications (2)

Publication Number Publication Date
JPS5789155A JPS5789155A (en) 1982-06-03
JPS6161428B2 true JPS6161428B2 (de) 1986-12-25

Family

ID=15824528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55166076A Granted JPS5789155A (en) 1980-11-25 1980-11-25 Integrated logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5789155A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
JPS62126367A (ja) * 1985-11-26 1987-06-08 Nec Corp 論理用集積回路
JP2608956B2 (ja) * 1989-06-14 1997-05-14 松下電子工業株式会社 半導体集積回路

Also Published As

Publication number Publication date
JPS5789155A (en) 1982-06-03

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