JPS6210390B2 - - Google Patents
Info
- Publication number
- JPS6210390B2 JPS6210390B2 JP54168645A JP16864579A JPS6210390B2 JP S6210390 B2 JPS6210390 B2 JP S6210390B2 JP 54168645 A JP54168645 A JP 54168645A JP 16864579 A JP16864579 A JP 16864579A JP S6210390 B2 JPS6210390 B2 JP S6210390B2
- Authority
- JP
- Japan
- Prior art keywords
- scan
- test
- memory element
- flip
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 87
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000010998 test method Methods 0.000 description 4
- 238000005192 partition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16864579A JPS5690271A (en) | 1979-12-25 | 1979-12-25 | Testing method for logic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16864579A JPS5690271A (en) | 1979-12-25 | 1979-12-25 | Testing method for logic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5690271A JPS5690271A (en) | 1981-07-22 |
JPS6210390B2 true JPS6210390B2 (de) | 1987-03-05 |
Family
ID=15871867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16864579A Granted JPS5690271A (en) | 1979-12-25 | 1979-12-25 | Testing method for logic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5690271A (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5859632A (ja) * | 1981-10-02 | 1983-04-08 | Matsushita Electronics Corp | 半導体集積回路 |
JPS643744A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Lsi test method |
-
1979
- 1979-12-25 JP JP16864579A patent/JPS5690271A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5690271A (en) | 1981-07-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7617425B2 (en) | Method for at-speed testing of memory interface using scan | |
JP4422427B2 (ja) | 単一チップシステム及びこのシステムのテスト/デバッグ方法 | |
US8156391B2 (en) | Data controlling in the MBIST chain architecture | |
KR100303618B1 (ko) | 셀프-타임식메모리어레이를갖는완전테스트가능한칩 | |
TW200424842A (en) | Method and apparatus for testing embedded cores | |
JPH05108396A (ja) | プロセツサ回路 | |
JPH0323871B2 (de) | ||
US6341092B1 (en) | Designing memory for testability to support scan capability in an asic design | |
US5339320A (en) | Architecture of circuitry for generating test mode signals | |
JPS6210390B2 (de) | ||
JPH08292237A (ja) | 2進データ出力インタフェース | |
KR0170210B1 (ko) | 메모리 장치의 테스트 회로 | |
JPH0432349B2 (de) | ||
JPS61217839A (ja) | スキヤン方式 | |
JPS6258025B2 (de) | ||
JPS63108747A (ja) | ゲ−トアレイ集積回路 | |
JPS6161428B2 (de) | ||
JPH026772A (ja) | 集積回路 | |
JP3024310B2 (ja) | 論理回路の検査装置 | |
JPS6248863B2 (de) | ||
SU1376121A2 (ru) | Устройство дл записи и контрол программируемой посто нной пам ти | |
JP2543119B2 (ja) | 論理回路のテスト方法 | |
JPH05334116A (ja) | デバッグ制御方式 | |
JPS5833581B2 (ja) | 診断に適した論理パッケ−ジ | |
JPH04328475A (ja) | 試験回路付半導体装置 |