JPS634211B2 - - Google Patents

Info

Publication number
JPS634211B2
JPS634211B2 JP55072247A JP7224780A JPS634211B2 JP S634211 B2 JPS634211 B2 JP S634211B2 JP 55072247 A JP55072247 A JP 55072247A JP 7224780 A JP7224780 A JP 7224780A JP S634211 B2 JPS634211 B2 JP S634211B2
Authority
JP
Japan
Prior art keywords
shift register
scan
memory
circuit
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55072247A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56168270A (en
Inventor
Koji Hashiguchi
Takeo Koizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7224780A priority Critical patent/JPS56168270A/ja
Publication of JPS56168270A publication Critical patent/JPS56168270A/ja
Publication of JPS634211B2 publication Critical patent/JPS634211B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP7224780A 1980-05-30 1980-05-30 Logical device Granted JPS56168270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7224780A JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7224780A JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Publications (2)

Publication Number Publication Date
JPS56168270A JPS56168270A (en) 1981-12-24
JPS634211B2 true JPS634211B2 (de) 1988-01-28

Family

ID=13483766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7224780A Granted JPS56168270A (en) 1980-05-30 1980-05-30 Logical device

Country Status (1)

Country Link
JP (1) JPS56168270A (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142432A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd シリアル・データ・スキャン・イン／アウト方法
JP2641739B2 (ja) * 1988-07-29 1997-08-20 富士通株式会社 試験装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113446A (en) * 1977-03-15 1978-10-03 Toshiba Corp Information processor and its method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113446A (en) * 1977-03-15 1978-10-03 Toshiba Corp Information processor and its method

Also Published As

Publication number Publication date
JPS56168270A (en) 1981-12-24

Similar Documents

Publication Publication Date Title
JP3890126B2 (ja) 集積回路のテスト用クロック発生方法および回路
JP2513904B2 (ja) テスト容易化回路
US6000051A (en) Method and apparatus for high-speed interconnect testing
JP4267716B2 (ja) Ｊｔａｇによるｓｄｒａｍ回路テスト方法
JPS62220879A (ja) 半導体装置
US5450418A (en) Pseudo master slave capture mechanism for scan elements
EP0632387A2 (de) Verfahren und Gerät zur Einfügung der Zustände nicht-abtastbarer Teile in einer Abtastkette
US6341092B1 (en) Designing memory for testability to support scan capability in an asic design
JPS634211B2 (de)
JP3094983B2 (ja) システムロジックのテスト回路およびテスト方法
KR20000069753A (ko) 코어 테스트 제어
US5426649A (en) Test interface for a digital circuit
EP1302776B1 (de) Automatische Abtastprüfung von komplexen integrierten Schaltungen
JPH06160489A (ja) バウンダリスキャン内部テスト方式
JPS6258025B2 (de)
JPS59211146A (ja) スキヤンイン方法
KR100503692B1 (ko) 고정논리값을출력하는수단의출력과회로의입력사이의접속테스팅장치
JPH0843494A (ja) 電子回路
JPH112664A (ja) バウンダリスキャンレジスタ
JPH0391195A (ja) メモリ回路
JPS6161428B2 (de)
JPH0389178A (ja) 半導体集積回路
EP0768538B2 (de) Verfahren und Tester zur Beaufschlagung eines elektronischen Bausteins mit einem Triggerimpuls
JPH11166961A (ja) バウンダリイスキャン回路
JPH02247586A (ja) 半導体集積回路装置