JPS6159860A - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法

Info

Publication number
JPS6159860A
JPS6159860A JP59181908A JP18190884A JPS6159860A JP S6159860 A JPS6159860 A JP S6159860A JP 59181908 A JP59181908 A JP 59181908A JP 18190884 A JP18190884 A JP 18190884A JP S6159860 A JPS6159860 A JP S6159860A
Authority
JP
Japan
Prior art keywords
package
module
chip
electrodes
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59181908A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0221139B2 (enrdf_load_stackoverflow
Inventor
Nobuhiko Aneba
姉歯　伸彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59181908A priority Critical patent/JPS6159860A/ja
Publication of JPS6159860A publication Critical patent/JPS6159860A/ja
Publication of JPH0221139B2 publication Critical patent/JPH0221139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP59181908A 1984-08-31 1984-08-31 半導体集積回路装置の製造方法 Granted JPS6159860A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181908A JPS6159860A (ja) 1984-08-31 1984-08-31 半導体集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181908A JPS6159860A (ja) 1984-08-31 1984-08-31 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6159860A true JPS6159860A (ja) 1986-03-27
JPH0221139B2 JPH0221139B2 (enrdf_load_stackoverflow) 1990-05-11

Family

ID=16108994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181908A Granted JPS6159860A (ja) 1984-08-31 1984-08-31 半導体集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS6159860A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392242A3 (en) * 1989-04-10 1991-12-11 International Business Machines Corporation Module assembly with intergrated semiconductor chip and chip carrier
EP0631691A4 (en) * 1992-03-16 1997-05-07 Dense Pac Microsystems Inc IC CHIP PACK AND MANUFACTURING METHOD.
US5833407A (en) * 1996-02-19 1998-11-10 Okuma Corporation Method for estimating heat-included displacment in a machine tool
EP1353374A1 (en) * 1990-09-24 2003-10-15 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
DE102007058870A1 (de) 2006-12-18 2008-07-24 Okuma Corporation Verfahren zum Erfassen der Anomalität eines Temperatursensors in einer Werkzeugmaschine
DE102007058871A1 (de) 2006-12-11 2008-08-28 Okuma Corporation Verfahren zum Erfassen der Anomalität eines Temperaturmessfühlers in einer Werkzeugmaschine
IT201900009660A1 (it) * 2019-06-20 2020-12-20 St Microelectronics Srl Dispositivo integrato a semiconduttore e procedimento per la fabbricazione di un dispositivo integrato a semiconduttore
WO2022090731A1 (en) * 2020-10-30 2022-05-05 Npl Management Limited Ion microtrap assembly and method of making of making such an assembly
US11389886B2 (en) 2018-10-19 2022-07-19 Sodick Co., Ltd. Electric discharge machining apparatus

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392242A3 (en) * 1989-04-10 1991-12-11 International Business Machines Corporation Module assembly with intergrated semiconductor chip and chip carrier
EP1353374A1 (en) * 1990-09-24 2003-10-15 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
EP0631691A4 (en) * 1992-03-16 1997-05-07 Dense Pac Microsystems Inc IC CHIP PACK AND MANUFACTURING METHOD.
US5833407A (en) * 1996-02-19 1998-11-10 Okuma Corporation Method for estimating heat-included displacment in a machine tool
DE102007058871A1 (de) 2006-12-11 2008-08-28 Okuma Corporation Verfahren zum Erfassen der Anomalität eines Temperaturmessfühlers in einer Werkzeugmaschine
DE102007058870A1 (de) 2006-12-18 2008-07-24 Okuma Corporation Verfahren zum Erfassen der Anomalität eines Temperatursensors in einer Werkzeugmaschine
US11389886B2 (en) 2018-10-19 2022-07-19 Sodick Co., Ltd. Electric discharge machining apparatus
IT201900009660A1 (it) * 2019-06-20 2020-12-20 St Microelectronics Srl Dispositivo integrato a semiconduttore e procedimento per la fabbricazione di un dispositivo integrato a semiconduttore
US11069587B2 (en) 2019-06-20 2021-07-20 Stmicroelectronics S.R.L. Integrated semiconductor device and process for manufacturing an integrated semiconductor device
WO2022090731A1 (en) * 2020-10-30 2022-05-05 Npl Management Limited Ion microtrap assembly and method of making of making such an assembly

Also Published As

Publication number Publication date
JPH0221139B2 (enrdf_load_stackoverflow) 1990-05-11

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