JPS6156623B2 - - Google Patents

Info

Publication number
JPS6156623B2
JPS6156623B2 JP58157808A JP15780883A JPS6156623B2 JP S6156623 B2 JPS6156623 B2 JP S6156623B2 JP 58157808 A JP58157808 A JP 58157808A JP 15780883 A JP15780883 A JP 15780883A JP S6156623 B2 JPS6156623 B2 JP S6156623B2
Authority
JP
Japan
Prior art keywords
lead
leads
small hole
frame
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58157808A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5956752A (ja
Inventor
Kanji Ootsuka
Eiji Yamamoto
Tamotsu Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58157808A priority Critical patent/JPS5956752A/ja
Publication of JPS5956752A publication Critical patent/JPS5956752A/ja
Publication of JPS6156623B2 publication Critical patent/JPS6156623B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49544Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58157808A 1983-08-31 1983-08-31 電子部品の製造方法 Granted JPS5956752A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58157808A JPS5956752A (ja) 1983-08-31 1983-08-31 電子部品の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58157808A JPS5956752A (ja) 1983-08-31 1983-08-31 電子部品の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP490977A Division JPS5390868A (en) 1977-01-21 1977-01-21 Semiconductor device of glass ceramic package type

Publications (2)

Publication Number Publication Date
JPS5956752A JPS5956752A (ja) 1984-04-02
JPS6156623B2 true JPS6156623B2 (en, 2012) 1986-12-03

Family

ID=15657735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58157808A Granted JPS5956752A (ja) 1983-08-31 1983-08-31 電子部品の製造方法

Country Status (1)

Country Link
JP (1) JPS5956752A (en, 2012)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321618A (ja) * 1986-07-15 1988-01-29 Olympus Optical Co Ltd 内視鏡
JPS6366525A (ja) * 1986-09-09 1988-03-25 Olympus Optical Co Ltd 電子内視鏡
JPS63274907A (ja) * 1987-05-06 1988-11-11 Olympus Optical Co Ltd ビデオ硬性内視鏡
JPH06148530A (ja) * 1993-06-07 1994-05-27 Olympus Optical Co Ltd 電子内視鏡

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7961454B2 (en) * 2005-05-18 2011-06-14 Sanyo Electric Co., Ltd. Multi-layered solid electrolytic capacitor and method of manufacturing same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321618A (ja) * 1986-07-15 1988-01-29 Olympus Optical Co Ltd 内視鏡
JPS6366525A (ja) * 1986-09-09 1988-03-25 Olympus Optical Co Ltd 電子内視鏡
JPS63274907A (ja) * 1987-05-06 1988-11-11 Olympus Optical Co Ltd ビデオ硬性内視鏡
JPH06148530A (ja) * 1993-06-07 1994-05-27 Olympus Optical Co Ltd 電子内視鏡

Also Published As

Publication number Publication date
JPS5956752A (ja) 1984-04-02

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