JPS5390868A - Semiconductor device of glass ceramic package type - Google Patents

Semiconductor device of glass ceramic package type

Info

Publication number
JPS5390868A
JPS5390868A JP490977A JP490977A JPS5390868A JP S5390868 A JPS5390868 A JP S5390868A JP 490977 A JP490977 A JP 490977A JP 490977 A JP490977 A JP 490977A JP S5390868 A JPS5390868 A JP S5390868A
Authority
JP
Japan
Prior art keywords
semiconductor device
glass ceramic
ceramic package
package type
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP490977A
Other languages
Japanese (ja)
Inventor
Kanji Otsuka
Eiji Yamamoto
Tamotsu Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP490977A priority Critical patent/JPS5390868A/en
Publication of JPS5390868A publication Critical patent/JPS5390868A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To reinforce the lead intensity at the small aperture part where the concentrated stress is produced, by increasing the shorter diameter of te small aperture of the lead frame through which the lead passes about 5 times as large as the thickness of the lead and filling the solder into the small aperture.
COPYRIGHT: (C)1978,JPO&Japio
JP490977A 1977-01-21 1977-01-21 Semiconductor device of glass ceramic package type Pending JPS5390868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP490977A JPS5390868A (en) 1977-01-21 1977-01-21 Semiconductor device of glass ceramic package type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP490977A JPS5390868A (en) 1977-01-21 1977-01-21 Semiconductor device of glass ceramic package type

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP58157808A Division JPS5956752A (en) 1983-08-31 1983-08-31 Manufacture of electronic component parts

Publications (1)

Publication Number Publication Date
JPS5390868A true JPS5390868A (en) 1978-08-10

Family

ID=11596759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP490977A Pending JPS5390868A (en) 1977-01-21 1977-01-21 Semiconductor device of glass ceramic package type

Country Status (1)

Country Link
JP (1) JPS5390868A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867056A (en) * 1981-10-19 1983-04-21 Toshiba Corp Lead frame for semiconductor device
JPS5867055A (en) * 1981-10-19 1983-04-21 Toshiba Corp Lead frame for semiconductor device
JPS58138352U (en) * 1982-03-12 1983-09-17 京セラ株式会社 Lead terminal for semiconductor package
JPS58215061A (en) * 1982-06-09 1983-12-14 Hitachi Ltd Semiconductor device and manufacture thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140478A (en) * 1975-05-30 1976-12-03 Hitachi Ltd Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140478A (en) * 1975-05-30 1976-12-03 Hitachi Ltd Lead frame

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867056A (en) * 1981-10-19 1983-04-21 Toshiba Corp Lead frame for semiconductor device
JPS5867055A (en) * 1981-10-19 1983-04-21 Toshiba Corp Lead frame for semiconductor device
JPS58138352U (en) * 1982-03-12 1983-09-17 京セラ株式会社 Lead terminal for semiconductor package
JPS58215061A (en) * 1982-06-09 1983-12-14 Hitachi Ltd Semiconductor device and manufacture thereof

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