JPS5956752A - Manufacture of electronic component parts - Google Patents
Manufacture of electronic component partsInfo
- Publication number
- JPS5956752A JPS5956752A JP58157808A JP15780883A JPS5956752A JP S5956752 A JPS5956752 A JP S5956752A JP 58157808 A JP58157808 A JP 58157808A JP 15780883 A JP15780883 A JP 15780883A JP S5956752 A JPS5956752 A JP S5956752A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- solder
- small holes
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
不発明はガラスセラミックパッケージ型半導体装置等の
１止された電子部品の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The invention relates to a method of manufacturing a single-piece electronic component such as a glass-ceramic packaged semiconductor device.
従来、ｌ、二とえば、ガラスヒラミックバック・−ジ型
半導併装１直にあっては、バック・−ジ部を形作るセラ
ミック板からなるキャップとベースはリードを間に挾み
、かつガラス層を介して接着されている。このガラス層
は外力に対しく弱く筒中にクラックを発生し７でしまう
。こσ）ため、組立にあ−′ｒは、あらかじめリード部
分が曲１１１シブ、ニリードフレ−１・を用いている。Conventionally, for example, in a glass ceramic back-ge type semiconductor mount, the cap and base made of ceramic plates that form the back-ge part sandwich the leads between them, and Bonded through a glass layer. This glass layer is weak against external forces and cracks occur inside the cylinder, resulting in failure. For this reason, for assembly, the reed part is made of a piece 111 and a piece of Ni lead frame 1 is used in advance.
しかし、曲折したｊ＋ −トルシー人は取扱いにくく、
かつ各部に詩１性がない、′−とか１う変形し易く、組
立精度がでにくい。し、た／（ζつ（、組立の自動化は
困難となる。However, the tortuous j + -Tulsis are difficult to handle;
In addition, each part lacks character, is easily deformed, and is difficult to assemble accurately. However, automation of assembly will be difficult.
そごで、リードの折り曲かり相当部がガラス層にクラッ
クが生じる外力よりも小さな外力で節片に折れ曲がイ）
ようにしておくことによって、平坦（フラット）なり一
ドフレーム享・用い、組立の自動化な図る方法が本出願
人によって提案されている。１なわら、リードを所定位
置で筒中に折れ曲かろようにするには、リードの所定位
（４にたどえば１形σ）孔を設けておき、リードの外端
に力を加えた際、この孔の周囲で応力４１４中が起きる
ように４−ろことによって、リードの伺しＪ゛根σガラ
ス層にクラックが生じる前に屈曲さ・毬ろものである。At that point, the portion of the lead that corresponds to the bending bends into a joint with an external force that is smaller than the external force that would cause a crack in the glass layer.
The present applicant has proposed a method of enjoying and using a flat frame and automating assembly by doing so. 1. However, in order to prevent the lead from bending into the cylinder at a predetermined position, a hole is provided at a predetermined position (1 type σ if you follow 4), so that when force is applied to the outer end of the lead, In order for the stress 414 to occur around this hole, the lead can be bent or curled before cracking occurs in the glass layer.
しかし、このようにして製造されたガラスセラミックパ
ッケージ型半導体装置にあっては、リードの応力集中箇
所は組立時においては組立の自動化を図る上で好都合で
あったが、完成品となった状態では逆に応力集中箇所で
簡単に曲がったり、あるいは折れたりすることになり、
好ましくない。However, in glass-ceramic packaged semiconductor devices manufactured in this way, stress concentration points on the leads are convenient for automating assembly during assembly, but in the finished product, On the other hand, it will easily bend or break at points where stress is concentrated.
Undesirable.
したが・って、本発明の目的は、リードの応力集中箇所
の強圧を補強したイ苺造のガラスセラミックパッケ−ジ
型半導体装置を提供１−ることにある。Therefore, an object of the present invention is to provide a glass-ceramic package type semiconductor device made of strawberries, which reinforces the strong pressure at stress concentration points of the leads.
このような目的を達成するために本発明は、リードの応
力集中を生じさせる孔部に金属、非金属等の物質を充満
させるものであって、以下実施例により本発明の詳細な
説明１°る。In order to achieve such an object, the present invention is to fill the holes that cause stress concentration in the lead with a substance such as a metal or a non-metal. Ru.
第１図（ａ）〜（Ｃ）は本発明のガラスセラミックパッ
ケージ型半導体装置の製造工程−実施例を示す。FIGS. 1(a) to 1(C) show an example of the manufacturing process of a glass-ceramic package type semiconductor device of the present invention.
同図（ａ）にはリードフレーム１が示されている。この
リードフレーム１は、１対の平行に延びる外枠２と、こ
れら外枠２を結ぶ１対の内枠３と、外枠２の内側から外
枠２と内枠３で形成される枠の中央部に向かって内枠３
に平行に延びるリード４とからなるとともに、各す−１
・”４Ｃ７）折曲相当部に小孔５を設は−しある、また
１、−れ［）小孔５はテ彰とフ、ｔｌ ｌ）、各折曲部
分が一定とノ）−）’ｒ、各ＩＪ −１・が整然と揃う
ようにな−）ていイ・。ｊまた。ｆｌリ−１４σ）小（
１，５かも外れた外枠側のり−１・＋’、ｌ’＝ ｉ）
−ｉ、ｌ ＃ＩＩｌい外部り・−ド６タ形作るとともに
、小孔５ ％’含む失陥部分し１．内部リード７享・形
ｆ’１−１−Ｃいイ）。土ｌへ内部り−ト７の先ψ：ｆ
Ｈ：を屈曲／、（、と１２（二枠σＭｌリコ部に臨ん−
て′ホ〕イ）７、また、省内部リード７θ）先端面によ
つ（四角のペレ、ｌ−取付空間８か形成されている。な
お、外枠２にはガイド孔９が殻（〕らオじＯいて、こσ
）ガイド孔９は位置決めやリ−）゛フレ・−ム１の送り
の際のガ・イドどし−Ｃ用いられイ）。A lead frame 1 is shown in FIG. This lead frame 1 includes a pair of outer frames 2 extending in parallel, a pair of inner frames 3 connecting these outer frames 2, and a frame formed by the outer frame 2 and the inner frame 3 from the inside of the outer frame 2. Inner frame 3 towards the center
and leads 4 extending parallel to each other.
・"4C7) The small hole 5 is set in the part corresponding to the bend. 'r, so that each IJ -1. is arranged in an orderly manner.
Glue on the outer frame side where 1 and 5 also came off -1・+', l' = i)
-i,l #IIlA small external diameter is formed, and a defective part containing 5% of small holes is formed.1. Internal lead 7 (form f'1-1-C). Internal route to soil l - beyond point 7 ψ: f
H: bend /, (, and 12 (two frames σMl Rico part -
7, In addition, a square plate, l-mounting space 8 is formed on the tip surface of the saving internal lead 7θ).In addition, a guide hole 9 is formed in the outer frame 2 through the shell (). RaojiO, here σ
) The guide hole 9 is used for positioning and as a guide when feeding the frame 1).
この、１：うなリードフレー、−、／、】に７１シ２、
下方からセラミック板からなるベース１０を上列させて
内部リード７に重ね合せる。ミーグ）際、ベース１０（
′）−上面にはガラスがＩＪ１１着され’Ｃｔ、；す、
かつ市ね＋３’ −ＩＬるとぎには加熱さ才じ（溶峙ｌ
ギれ？八・る。しｔこかって、市ね台・毬て冷却Ｊるこ
とにコつて、ベース１０は内部り一１’ ７と一体化ず
ろ。庄に、こσ）ペース取・ｆ＝Ｊ時にペレッｌ取伺空
間））に対応するベース１０上に回路素子を形成し７た
ベレット１１を同様にガラス層を介して固定する。This, 1: Una Lead Fray, -, /, ] 71 shi 2,
Bases 10 made of ceramic plates are arranged in an upper row from below and overlapped with internal leads 7. Meeg), base 10 (
') - Glass is attached to the top surface 'Ct;
Katsuichine+3' -IL Togi is heated
Gire? 8.ru. For this reason, the base 10 should be integrated with the internal plate 1'7 in order to cool the market and the container. Then, a circuit element is formed on the base 10 corresponding to the space σ) paced when f=J and the pellet 11 is similarly fixed via a glass layer.
つぎに、リードフレーノー １ ＆’１次の工程に送ら
れ、ペレット１．１の各市、極と各内部リードの先端と
が１ノイーＶ″Ｃ接続される１、さらに、リートフ１／
−ノ・１は次σ几＋Ｘ程に運ばれ、ベース１（）上にキ
ャップ１２か小ねｆｌされるとともに、加熱炉に入れｌ
））ｇ ′ｃ気密刊止が行なわれる。前記キャップ１２
１１ベース１０と同じ大きさσ片ヒラミ・ツク板か１′
−）プＪ：るどともに、下面中央部は部み、べ・−ス］
、ＯＬＫ爪ねられた際、べ１・′ット衣面やワイヤに接
触しないようにＩＪ２つ′で、いる。また、・Ｖヤノプ
１２の−Ｆ面枠部（」ガラスが剛着され゛（いる１、［
、たがっ又、加熱炉に人オ口ろれるど、べ・−スＪＯお
よびギャップ１２のガラスが溶１Ａ′μし−１一体化す
るため、′冷却に」：ってリー ドど一体化する。Next, the pellet 1.1 is sent to the next process, where each pole of the pellet 1.1 and the tip of each internal lead are connected to the tip of each internal lead by 1 V''C.
-No.1 is then transported to about σ +
)) g 'c An airtight stop is performed. The cap 12
11 Base same size as 10 σ piece Hirami Tsuku board or 1'
-) Pu J: With Rudo, the center part of the lower surface is bent, base]
If the OLK's nail is pinched, use two IJ's to prevent it from coming into contact with the bed surface or wires. In addition, the glass is firmly attached to the -F side frame part of V Yanop 12.
However, when the heating furnace is heated, the base JO and the glass in the gap 12 are melted at 1A'μ and are integrated into one, so the leads are integrated for cooling. .
１）ぎ区−１図図（ａ）のＱ、Ｈで示すように、外部り
−１゛６のりｌ枠１との伺は根部分−（ヨ切断するとと
もに、凹型等を用い、同図（１））で示す」、５にリー
ド４毛・小孔５のある折曲部で折り曲げる。1) As shown by Q and H in Fig. 1 (a), the outer edge - 1゛6 glue l frame 1 should be cut at the root part (Yo), and using a concave mold etc. (1)), 5, bend at the bending part where the lead 4 and the small hole 5 are located.
以」二の各組立加工作業は、ＩＪ −ドフレーム１がフ
ラットであることから筒中に自動化できる。The following two assembly operations can be automated in the cylinder since the IJ-deframe 1 is flat.
その後、同図（ｂ）で示−３卸品を１１４田液中に浸漬
（ディップ）し、ベース１０お、１、びヤーヤ・ノブ】
２とからなるバックージ部】３か１゛９突出するりニド
４０表面に半１Ｂをｌ’ｆＪ着さ一毬て同ヒ；（Ｃ）で
示すガラスセラミ・クパッケージ型半導体４’１Ｍ−１
４を゛製造する。このような半田ディノプケ施こ−Ｊこ
とにより、ε（ｒ、 ２図（ａ）で示すように、リ−１
・４にイＪ在していた小孔５には、同図０〕）で示すよ
うに半■１１５が入り込みブリッジし、小孔５を塞ぐ、
この結果、応力１朽中は極めて少ｉｔ くなることか１
０）、名リード４の強１隻は同上する。また、各り−１
４の表１ｆ４ｉにも半田被膜１６が形成されることから
、ガラスセラミ・クパッケージ型半導体装１６の取付時
の半Ｈ１の屑れが良＜７．【る。なお、小孔５を確実に
−塞ぐためには、小孔５の幅りはリード４のｊψさの最
大５倍前後までとする必要がある。ｌ；＋Ｉ「Ｊるなら
ば、５倍Ｊ、Ｊ上となると、半田＆」ブリッジ苓形１１
υ、しに＜＜ｈり小孔５は完全に塞げ１．ｃい。そＬ７
て、中央部には孔が生じ１本来の半田被膜による補強が
なされないことに１４る。Thereafter, the product shown in Figure (b) was dipped in 114 rice liquid, and the base 10,
[Backage part consisting of 2] 3 or 1゛9 Deposit half 1B on the surface of the protruding diode 40 and do the same; Glass ceramic package type semiconductor 4'1M-1 shown in (C)
Manufacture 4. By applying such soldering, ε(r, as shown in Figure 2(a),
・As shown in Figure 0]), half 115 enters the small hole 5 that was present in 4 and bridges it, closing the small hole 5.
As a result, it becomes extremely small during stress decay1.
0), one strong ship with a name lead of 4 is the same as above. Also, each -1
Since the solder film 16 is also formed in Table 1f4i of Table 1f4, the amount of debris on the half H1 when the glass-ceramic package type semiconductor device 16 is attached is good. [ru. In order to reliably close the small hole 5, the width of the small hole 5 needs to be approximately five times the width of the lead 4 at most. l;+I "If J is 5 times J, if it is above J, solder &" Bridge Reigata 11
υ, the small hole 5 should be completely closed.1. It's ugly. So L7
As a result, a hole is formed in the center part, and the original solder coating cannot be used for reinforcement.
このような実施例によれば、組立時にはリードの孔を有
−Ｊる応力集中部を利用することによってフラットなリ
ードフレート、を用いて組立の自動化を図るとともに１
組立加工が終了１〜た時点では、リード全ＩＲ−ｔに半
田ディツプすることによって小孔を塞ぎ、リードの強度
を増大している。したがって、ガラスセラミックパンケ
ージ型半導体装置の取扱時にリードが曲かったり、折れ
たりすることはない。According to such an embodiment, during assembly, assembly is automated by using a flat lead plate by utilizing a stress concentration part having a hole in the lead.
When the assembly process is completed 1~, all the leads IR-t are dipped with solder to close the small holes and increase the strength of the leads. Therefore, the leads will not be bent or broken during handling of the glass ceramic pancage type semiconductor device.
なお、本発明は前記実施例に限定されない。たどえし」
：、小孔には欽等の金属シデ７ｆソノして塞いでもよい
。まノこ、ガラスやフ“ラスチックを塗布し２て充填し
゛〔も」；い。Note that the present invention is not limited to the above embodiments. Tadoeshi”
: The small hole may be plugged with a metal horn such as a 7F piece. It can also be filled with glass or plastic.
さＩ−）［、リードに設ける小孔の形状、数は第３図（
ａ）〜（ｆ）に示すようなものでよ）ってもよい。The shape and number of small holes provided in the lead are shown in Figure 3 (
Those shown in a) to (f) may also be used.
以十の」、うに、本発明適用Ｌ７たガラスセラミ・クバ
ノクージ型半導体装置、竹にリードに小孔を設け、この
小孔部でリード乞折り曲げた構造の半導体装置において
、前記小孔部（？−物ｒ１な充滴達えであることかＩ−
）、ごの部分の「；パｌ１ｌｔ′ｌ−か回」−するσつ
で、従来の半導体装置よりもリ −ド強ＦＷが向上する
。In a glass-ceramic Kubanokuji type semiconductor device to which the present invention is applied, a small hole is provided in a bamboo lead, and the lead is bent at the small hole. -Is it that the thing r1 is reaching the full charge?I-
), the lead strength FW is improved compared to the conventional semiconductor device.
第１図（ａ）−（ｃ）は本発明のノ゛Ｊう、スｌ−フミ
ソクノ９Ｉり“−ジ型半導体装置の製造ｌ程も示−Ｊ’
ＬＴへ一１゛・１、第２図（ａ）、 （ｂ）は同じく各
工程１１１−ｔ６し」ろ断面１す３１、第３１・′／Ｉ
（ａ）〜（「）はり・−１゛における応力ＩＢ ｒｉ１
享′生じさせる孔の形状を示す一部３１′而図７晃躯、
。
■・・リードフレート、２−・夕を枠、；３・・・内枠
、４・・・リード、５・・・小孔、６・・・り１部す−
ド、７・・・内部リー暑、８・・ペレットＪｌｌ／、
伺空間、９・・ガイド孔、１０・・・べ・−ス、１１・
・・ペレノ１１１２・・八Ｙ・ノ：７゛、】３・・・バ
ノクージ部、１４・・・ガラス−１ニラミノクツ＜ノケ
ージ型°１へ導付装（ｒｌ、１５・・・半ＩＴＩ、１６
・・・半ＦＦＩ被月１１゜
代理人 弁理士 高 橋 明 失
策 １ 図
第 ２ 図
とσ−） （句
第 ３ 図
（ぬ） （、ａ）
（ｄ） （ｅ）
（Ｃ）
（ヂ）FIGS. 1(a) to 1(c) also show the manufacturing process of a sulfur type semiconductor device according to the present invention.
LT to 11゛・1, Figure 2 (a) and (b) are the same for each step 111-t6.
(a) - Stress at beam -1゛ IB ri1
Part 31' showing the shape of the hole to be produced, and Figure 7.
. ■...Lead plate, 2--evening frame; 3...inner frame, 4...lead, 5...small hole, 6...ri 1 part-
Do, 7...internal heat, 8...pellet Jll/,
Visiting space, 9...Guide hole, 10...Base, 11.
・・Pereno 1112・・8Y・ノ：7゛、】3...Banokuji part, 14...Glass-1 Niraminokutsu<No cage type °1 Induction equipment (rl, 15...Half ITI, 16
... Half-FFI month 11゜ Agent Patent attorney Akira Takahashi Mistake 1 Figure 2 and σ-) (phrase Figure 3 (nu) (, a) (d) (e) (C) (ヂ)
Claims (1)
ほぼ平坦な所定σ）パターンを有するリードフレームの
主蟹部を封止部利により封止する］二程（ｂｌ １１
−ドの曲げられイ）べき部分に設けられた欠陥部分の近
傍、で上記す・−１・３所定形状に曲げ形成する−［程 （Ｃ１上記欠陥部分に充填部利な充填する工程（（１）
上記リードフレームから素子を含む部分を分離′ｒる」
二程 の名］−稈より１する１１７．子部品の製造方法。[Claims] 1. (a) The element and the main part of the lead frame having a substantially flat predetermined σ pattern electrically connected thereto are sealed by a sealing part.
- Step (C1) Filling the defective part with a filling part (C1) In the vicinity of the defective part in the part to be bent, 1)
Separate the part containing the element from the lead frame.
Second name] - 1 from the culm 117. How to manufacture child parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157808A JPS5956752A (en) | 1983-08-31 | 1983-08-31 | Manufacture of electronic component parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157808A JPS5956752A (en) | 1983-08-31 | 1983-08-31 | Manufacture of electronic component parts |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP490977A Division JPS5390868A (en) | 1977-01-21 | 1977-01-21 | Semiconductor device of glass ceramic package type |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5956752A true JPS5956752A (en) | 1984-04-02 |
| JPS6156623B2 JPS6156623B2 (en) | 1986-12-03 |
Family
ID=15657735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157808A Granted JPS5956752A (en) | 1983-08-31 | 1983-08-31 | Manufacture of electronic component parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5956752A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961454B2 (en) * | 2005-05-18 | 2011-06-14 | Sanyo Electric Co., Ltd. | Multi-layered solid electrolytic capacitor and method of manufacturing same |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6321618A (en) * | 1986-07-15 | 1988-01-29 | Olympus Optical Co Ltd | Endoscope |
| JPS6366525A (en) * | 1986-09-09 | 1988-03-25 | Olympus Optical Co Ltd | Electronic endoscope |
| JPS63274907A (en) * | 1987-05-06 | 1988-11-11 | Olympus Optical Co Ltd | Video hard endoscope |
| JPH06148530A (en) * | 1993-06-07 | 1994-05-27 | Olympus Optical Co Ltd | Electronic endoscope |
-
1983
- 1983-08-31 JP JP58157808A patent/JPS5956752A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961454B2 (en) * | 2005-05-18 | 2011-06-14 | Sanyo Electric Co., Ltd. | Multi-layered solid electrolytic capacitor and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6156623B2 (en) | 1986-12-03 |
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