JPS6152596B2 - - Google Patents
Info
- Publication number
- JPS6152596B2 JPS6152596B2 JP56085907A JP8590781A JPS6152596B2 JP S6152596 B2 JPS6152596 B2 JP S6152596B2 JP 56085907 A JP56085907 A JP 56085907A JP 8590781 A JP8590781 A JP 8590781A JP S6152596 B2 JPS6152596 B2 JP S6152596B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- forming
- region
- substantially vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
- H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/167,253 US4359816A (en) | 1980-07-08 | 1980-07-08 | Self-aligned metal process for field effect transistor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5745281A JPS5745281A (en) | 1982-03-15 |
| JPS6152596B2 true JPS6152596B2 (enFirst) | 1986-11-13 |
Family
ID=22606587
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56085907A Granted JPS5745281A (en) | 1980-07-08 | 1981-06-05 | Method of producing field effect transistor |
| JP56110983A Expired JPS5831734B2 (ja) | 1980-07-08 | 1981-07-17 | 半導体メモリ装置の製造方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56110983A Expired JPS5831734B2 (ja) | 1980-07-08 | 1981-07-17 | 半導体メモリ装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4359816A (enFirst) |
| EP (1) | EP0043943B1 (enFirst) |
| JP (2) | JPS5745281A (enFirst) |
| CA (1) | CA1169585A (enFirst) |
| DE (1) | DE3175618D1 (enFirst) |
Families Citing this family (67)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4400865A (en) * | 1980-07-08 | 1983-08-30 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
| US4471522A (en) * | 1980-07-08 | 1984-09-18 | International Business Machines Corporation | Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes |
| US4758528A (en) * | 1980-07-08 | 1988-07-19 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
| US4688073A (en) * | 1981-03-30 | 1987-08-18 | Goth George R | Lateral device structures using self-aligned fabrication techniques |
| US4508579A (en) * | 1981-03-30 | 1985-04-02 | International Business Machines Corporation | Lateral device structures using self-aligned fabrication techniques |
| US4743565A (en) * | 1981-03-30 | 1988-05-10 | International Business Machines Corporation | Lateral device structures using self-aligned fabrication techniques |
| US4455738A (en) * | 1981-12-24 | 1984-06-26 | Texas Instruments Incorporated | Self-aligned gate method for making MESFET semiconductor |
| US4553316A (en) * | 1981-12-24 | 1985-11-19 | Texas Instruments Incorporated | Self-aligned gate method for making MESFET semiconductor |
| US4424621A (en) | 1981-12-30 | 1984-01-10 | International Business Machines Corporation | Method to fabricate stud structure for self-aligned metallization |
| US4430791A (en) * | 1981-12-30 | 1984-02-14 | International Business Machines Corporation | Sub-micrometer channel length field effect transistor process |
| US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
| US4445267A (en) * | 1981-12-30 | 1984-05-01 | International Business Machines Corporation | MOSFET Structure and process to form micrometer long source/drain spacing |
| JPS58158972A (ja) * | 1982-03-16 | 1983-09-21 | Toshiba Corp | 半導体装置の製造方法 |
| FR2525029A1 (fr) * | 1982-04-08 | 1983-10-14 | Commissariat Energie Atomique | Procede d'isolation d'une ligne conductrice dans un circuit integre et procede de fabrication d'un transistor mos utilisant un tel procede d'isolation |
| JPS58184765A (ja) * | 1982-04-23 | 1983-10-28 | Fujitsu Ltd | 半導体装置の製造方法 |
| DE3242113A1 (de) * | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
| JPS59114871A (ja) * | 1982-12-21 | 1984-07-03 | Toshiba Corp | シヨツトキ−ゲ−ト型GaAs電界効果トランジスタの製造方法 |
| JPS59124172A (ja) * | 1982-12-30 | 1984-07-18 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Fet製造方法 |
| US4542577A (en) * | 1982-12-30 | 1985-09-24 | International Business Machines Corporation | Submicron conductor manufacturing |
| US4532532A (en) * | 1982-12-30 | 1985-07-30 | International Business Machines Corporation | Submicron conductor manufacturing |
| JPS59181614A (ja) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | 半導体装置の製造方法 |
| JPS6070768A (ja) * | 1983-09-27 | 1985-04-22 | Toshiba Corp | 電界効果トランジスタの製造方法 |
| US4636834A (en) * | 1983-12-12 | 1987-01-13 | International Business Machines Corporation | Submicron FET structure and method of making |
| US4551906A (en) * | 1983-12-12 | 1985-11-12 | International Business Machines Corporation | Method for making self-aligned lateral bipolar transistors |
| US4546535A (en) * | 1983-12-12 | 1985-10-15 | International Business Machines Corporation | Method of making submicron FET structure |
| JPS60137070A (ja) * | 1983-12-26 | 1985-07-20 | Toshiba Corp | 半導体装置の製造方法 |
| FR2568723B1 (fr) * | 1984-08-03 | 1987-06-05 | Commissariat Energie Atomique | Circuit integre notamment de type mos et son procede de fabrication |
| US4641420A (en) * | 1984-08-30 | 1987-02-10 | At&T Bell Laboratories | Metalization process for headless contact using deposited smoothing material |
| US4939154A (en) * | 1987-03-25 | 1990-07-03 | Seiko Instruments Inc. | Method of fabricating an insulated gate semiconductor device having a self-aligned gate |
| US4803173A (en) * | 1987-06-29 | 1989-02-07 | North American Philips Corporation, Signetics Division | Method of fabrication of semiconductor device having a planar configuration |
| US4868138A (en) * | 1988-03-23 | 1989-09-19 | Sgs-Thomson Microelectronics, Inc. | Method for forming a self-aligned source/drain contact for an MOS transistor |
| FR2634318B1 (fr) * | 1988-07-13 | 1992-02-21 | Commissariat Energie Atomique | Procede de fabrication d'une cellule de memoire integree |
| US5079180A (en) * | 1988-12-22 | 1992-01-07 | Texas Instruments Incorporated | Method of fabricating a raised source/drain transistor |
| US4945070A (en) * | 1989-01-24 | 1990-07-31 | Harris Corporation | Method of making cmos with shallow source and drain junctions |
| US4895520A (en) * | 1989-02-02 | 1990-01-23 | Standard Microsystems Corporation | Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant |
| US5001082A (en) * | 1989-04-12 | 1991-03-19 | Mcnc | Self-aligned salicide process for forming semiconductor devices and devices formed thereby |
| US5231040A (en) * | 1989-04-27 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a field effect transistor |
| US4948745A (en) * | 1989-05-22 | 1990-08-14 | Motorola, Inc. | Process for elevated source/drain field effect structure |
| US4980018A (en) * | 1989-11-14 | 1990-12-25 | Intel Corporation | Plasma etching process for refractory metal vias |
| US5013680A (en) * | 1990-07-18 | 1991-05-07 | Micron Technology, Inc. | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography |
| US5177027A (en) * | 1990-08-17 | 1993-01-05 | Micron Technology, Inc. | Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path |
| JPH04280436A (ja) * | 1990-09-28 | 1992-10-06 | Motorola Inc | 相補型自己整合hfetの製造方法 |
| US5385850A (en) * | 1991-02-07 | 1995-01-31 | International Business Machines Corporation | Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer |
| US5250450A (en) * | 1991-04-08 | 1993-10-05 | Micron Technology, Inc. | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance |
| US5122848A (en) * | 1991-04-08 | 1992-06-16 | Micron Technology, Inc. | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance |
| US5466636A (en) * | 1992-09-17 | 1995-11-14 | International Business Machines Corporation | Method of forming borderless contacts using a removable mandrel |
| KR100206876B1 (ko) * | 1995-12-28 | 1999-07-01 | 구본준 | 모스전계효과트랜지스터 제조방법 |
| JPH08250486A (ja) * | 1996-03-08 | 1996-09-27 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| US5804846A (en) * | 1996-05-28 | 1998-09-08 | Harris Corporation | Process for forming a self-aligned raised source/drain MOS device and device therefrom |
| US5811339A (en) * | 1996-09-11 | 1998-09-22 | Vanguard International Semiconductor Corporation | Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon |
| US6063675A (en) * | 1996-10-28 | 2000-05-16 | Texas Instruments Incorporated | Method of forming a MOSFET using a disposable gate with a sidewall dielectric |
| US5950091A (en) * | 1996-12-06 | 1999-09-07 | Advanced Micro Devices, Inc. | Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material |
| TW358989B (en) * | 1997-04-08 | 1999-05-21 | United Microelectronics Corp | Method of forming gold-oxygen semiconductor cells |
| US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
| US6127232A (en) * | 1997-12-30 | 2000-10-03 | Texas Instruments Incorporated | Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions |
| US5915183A (en) * | 1998-06-26 | 1999-06-22 | International Business Machines Corporation | Raised source/drain using recess etch of polysilicon |
| US5998847A (en) * | 1998-08-11 | 1999-12-07 | International Business Machines Corporation | Low voltage active body semiconductor device |
| JP3748726B2 (ja) * | 1999-01-28 | 2006-02-22 | シャープ株式会社 | 量子細線の製造方法 |
| CN1610063A (zh) * | 2003-10-24 | 2005-04-27 | 上海宏力半导体制造有限公司 | 形成栅极结构的方法 |
| GB2423634A (en) * | 2005-02-25 | 2006-08-30 | Seiko Epson Corp | A patterning method for manufacturing high resolution structures |
| JP2008288499A (ja) * | 2007-05-21 | 2008-11-27 | Panasonic Corp | 半導体装置及びその製造方法 |
| US9601630B2 (en) * | 2012-09-25 | 2017-03-21 | Stmicroelectronics, Inc. | Transistors incorporating metal quantum dots into doped source and drain regions |
| US9748356B2 (en) | 2012-09-25 | 2017-08-29 | Stmicroelectronics, Inc. | Threshold adjustment for quantum dot array devices with metal source and drain |
| CN103855003B (zh) * | 2012-11-28 | 2017-11-21 | 中国科学院微电子研究所 | 半导体器件制造方法 |
| US10002938B2 (en) | 2013-08-20 | 2018-06-19 | Stmicroelectronics, Inc. | Atomic layer deposition of selected molecular clusters |
| US10224407B2 (en) * | 2017-02-28 | 2019-03-05 | Sandisk Technologies Llc | High voltage field effect transistor with laterally extended gate dielectric and method of making thereof |
| DE102018132237B4 (de) * | 2018-12-14 | 2025-02-06 | Infineon Technologies Ag | Leistungshalbleitervorrichtungen und Verfahren zu deren Herstellung |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3643235A (en) * | 1968-12-30 | 1972-02-15 | Ibm | Monolithic semiconductor memory |
| US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
| US3750268A (en) * | 1971-09-10 | 1973-08-07 | Motorola Inc | Poly-silicon electrodes for c-igfets |
| JPS4859781A (enFirst) * | 1971-11-25 | 1973-08-22 | ||
| DE2212168C2 (de) * | 1972-03-14 | 1982-10-21 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte Halbleiteranordnung |
| DE2262297C2 (de) * | 1972-12-20 | 1985-11-28 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau |
| US4055885A (en) * | 1973-02-28 | 1977-11-01 | Hitachi, Ltd. | Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the same |
| GB1477512A (en) * | 1974-05-21 | 1977-06-22 | Mullard Ltd | Methods of manufacturing semiconductor devices |
| US3984822A (en) * | 1974-12-30 | 1976-10-05 | Intel Corporation | Double polycrystalline silicon gate memory device |
| GB1527894A (en) * | 1975-10-15 | 1978-10-11 | Mullard Ltd | Methods of manufacturing electronic devices |
| US4295264A (en) * | 1975-12-29 | 1981-10-20 | Texas Instruments Incorporated | Method of making integrated circuit MOS capacitor using implanted region to change threshold |
| US4053349A (en) * | 1976-02-02 | 1977-10-11 | Intel Corporation | Method for forming a narrow gap |
| US4075045A (en) * | 1976-02-09 | 1978-02-21 | International Business Machines Corporation | Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps |
| US4103415A (en) * | 1976-12-09 | 1978-08-01 | Fairchild Camera And Instrument Corporation | Insulated-gate field-effect transistor with self-aligned contact hole to source or drain |
| US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
| GB2003660A (en) | 1977-08-19 | 1979-03-14 | Plessey Co Ltd | Deposition of material on a substrate |
| US4190466A (en) * | 1977-12-22 | 1980-02-26 | International Business Machines Corporation | Method for making a bipolar transistor structure utilizing self-passivating diffusion sources |
| US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
| US4234362A (en) * | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
| US4209350A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming diffusions having narrow dimensions utilizing reactive ion etching |
| US4256514A (en) * | 1978-11-03 | 1981-03-17 | International Business Machines Corporation | Method for forming a narrow dimensioned region on a body |
| US4249968A (en) * | 1978-12-29 | 1981-02-10 | International Business Machines Corporation | Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers |
| US4222164A (en) * | 1978-12-29 | 1980-09-16 | International Business Machines Corporation | Method of fabrication of self-aligned metal-semiconductor field effect transistors |
| US4236294A (en) * | 1979-03-16 | 1980-12-02 | International Business Machines Corporation | High performance bipolar device and method for making same |
| US4287661A (en) * | 1980-03-26 | 1981-09-08 | International Business Machines Corporation | Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation |
-
1980
- 1980-07-08 US US06/167,253 patent/US4359816A/en not_active Expired - Lifetime
-
1981
- 1981-06-05 JP JP56085907A patent/JPS5745281A/ja active Granted
- 1981-06-15 CA CA000379794A patent/CA1169585A/en not_active Expired
- 1981-06-23 EP EP81104805A patent/EP0043943B1/en not_active Expired
- 1981-06-23 DE DE8181104805T patent/DE3175618D1/de not_active Expired
- 1981-07-17 JP JP56110983A patent/JPS5831734B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5831734B2 (ja) | 1983-07-08 |
| CA1169585A (en) | 1984-06-19 |
| DE3175618D1 (en) | 1987-01-02 |
| JPS57115862A (en) | 1982-07-19 |
| EP0043943A2 (en) | 1982-01-20 |
| EP0043943A3 (en) | 1983-01-26 |
| JPS5745281A (en) | 1982-03-15 |
| EP0043943B1 (en) | 1986-11-12 |
| US4359816A (en) | 1982-11-23 |
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