JPS6148950A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS6148950A
JPS6148950A JP59170889A JP17088984A JPS6148950A JP S6148950 A JPS6148950 A JP S6148950A JP 59170889 A JP59170889 A JP 59170889A JP 17088984 A JP17088984 A JP 17088984A JP S6148950 A JPS6148950 A JP S6148950A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
frame
frame body
heat dissipating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59170889A
Other languages
English (en)
Inventor
Hisanori Yamashita
尚徳 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59170889A priority Critical patent/JPS6148950A/ja
Publication of JPS6148950A publication Critical patent/JPS6148950A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体集積回路装置の構造に関するものである
。
〔従来技術〕
従来の集積回路は放熱性を良くするために集積回路チッ
プ全放熱板に載置し、この放熱板に半導体チップ封止の
ための枠体を設けたものがある。
この例を第２図に示す、放熱板２上に集積回路チ、プ３
ｔ−取力付け、集積回路チップ３ｔ−囲むように枠体１
を放熱板２上に取力付けている。枠体１上表面にはメタ
ライズ面を有し、このメタライズ面に集積回路チップ３
の電極との接続のため、金属細線を取っ付けた後、枠体
１上に更に樹脂枠５金設は封止樹脂４で封止している。
全体は回路基板７に半田６で取フ付けられる。
（発明が解決しようとする問題点） かかる集積回路では枠体１が放熱板２の外側に張力比し
ており、しかもこの部分の下は空間になっているため１
回路基板７に放熱体２を取っ付けた時極めて不安定で実
装がむづかしいという欠点があった。また、枠体１が完
全に放熱板２の上方にあるので全体の厚さが厚くなると
いう欠点もあった。
（問題点を解決するための手段） 本発明によれば、集積回路チップの取っ付けられた放熱
板に集積回路チップを取力囲む枠体を取り付け、この枠
体に放熱板がはまる大きさの座グＶｔ設け、もって放熱
板底面と枠体の底面とを同一平面とした集積回路装ＷＬ
ｔ−得る。
（実施例） 次に１図面を参照して本発明をよフ詳細に説明する。
第１図は本発明の一実施例を示したもので、集積回路チ
ップ３は放熱板２上に取〃付けられている。集積回路チ
ップ３を囲み放熱板２に取り付けられた枠体１１は下面
内部に放熱板２ｔ−Ｈめ込む大きさの座ぐｌ−有してい
る。この座ぐりの中に放熱板２がはめ込まれている。枠
体１１の上表面には集積回路チップ３の電極導出のため
の配線が設けられている。この配線と集積回路チップ３
の電極間は金属細線で接続されている。枠体１１上には
更に集積回路チップ３を囲む樹脂枠５が設けられている
。配線の終った集積回路チップ３は封止樹脂４で封止さ
れている。枠体１１は回路基板７に半田６で取フ付けら
れている。
（発明の効果） この工うに、本発明によれば枠体１１に放熱板２をはめ
込む座グリが設けられているので、枠体１１と放熱板２
との底面は同一平面を形成しておシ１回路基板７へ取フ
付ける時も安定して行うことができる。また、枠体１１
と放熱板２とはその厚さが一部で重っているので全体の
厚さも薄くできる。
【図面の簡単な説明】
第１図は本発明の一実施例を示す断面図である。 第２図は従来の集積回路装置を示す断面図である。 １．１１・・・、・・・枠体、２・・・・・・放熱板、
３・・・・・・集積回路チップ、４・・・・・・封止樹
脂、５・・・・・・樹Ｈ旨枠、６・・・・・・半田、７
・・・・・・回路基板。

Claims (1)

    【特許請求の範囲】
  1. 半導体基板裏面に放熱板を有し、前記半導体基板の周囲
    を囲み一部が前記放熱板上に載置され枠体を備え、該枠
    体の下面は座グリを設けることによって前記放熱板の下
    面と同一表面のなしていることを特徴とする集積回路装
    置。
JP59170889A 1984-08-16 1984-08-16 集積回路装置 Pending JPS6148950A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59170889A JPS6148950A (ja) 1984-08-16 1984-08-16 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59170889A JPS6148950A (ja) 1984-08-16 1984-08-16 集積回路装置

Publications (1)

Publication Number Publication Date
JPS6148950A true JPS6148950A (ja) 1986-03-10

Family

ID=15913194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59170889A Pending JPS6148950A (ja) 1984-08-16 1984-08-16 集積回路装置

Country Status (1)

Country Link
JP (1) JPS6148950A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5885853A (en) * 1990-06-22 1999-03-23 Digital Equipment Corporation Hollow chip package and method of manufacture

Similar Documents

Publication Publication Date Title
KR100307465B1 (ko) 파워모듈
US3469017A (en) Encapsulated semiconductor device having internal shielding
JPH03108744A (ja) 樹脂封止型半導体装置
JP2003115681A (ja) 電子部品の実装構造
JPH0773122B2 (ja) 封止型半導体装置
JPS6148950A (ja) 集積回路装置
JP2779537B2 (ja) フィン付き電子部品搭載用基板
JPH0382060A (ja) 半導体装置
JP2795063B2 (ja) 混成集積回路装置
JPH06112674A (ja) 電子部品搭載装置用のヒートシンク
JPH0732216B2 (ja) 半導体装置
KR970053677A (ko) 히트싱크가 부착된 컬럼형 패키지
JP2778790B2 (ja) 半導体装置の実装構造及び実装方法
JPH0497554A (ja) 高放熱型半導体パッケージ
JPH06104356A (ja) 表面実装型半導体装置
JPH0685102A (ja) 半導体集積回路装置
JPH02119247A (ja) ピングリッドアレイパッケージ型半導体装置
JP2006024639A (ja) 半導体装置
JPS60138945A (ja) 封止型半導体装置
JPH01273340A (ja) 樹脂封止型半導体装置
JP2522583Y2 (ja) 放熱フイン付きジヤンパ線ユニツト
JPH0442930Y2 (ja)
JP2000133911A (ja) 電子部品搭載装置
JPH0414852A (ja) 半導体装置
JPH0758160A (ja) フィルムキャリヤ及びこのフィルムキャリヤを用いた半導体装置