JPS60138945A - 封止型半導体装置 - Google Patents

封止型半導体装置

Info

Publication number
JPS60138945A
JPS60138945A JP58244557A JP24455783A JPS60138945A JP S60138945 A JPS60138945 A JP S60138945A JP 58244557 A JP58244557 A JP 58244557A JP 24455783 A JP24455783 A JP 24455783A JP S60138945 A JPS60138945 A JP S60138945A
Authority
JP
Japan
Prior art keywords
radiating fin
soldered
semiconductor device
sealed semiconductor
envelope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58244557A
Other languages
English (en)
Other versions
JPH0714021B2 (ja
Inventor
Hiromichi Sawatani
沢谷　博道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58244557A priority Critical patent/JPH0714021B2/ja
Publication of JPS60138945A publication Critical patent/JPS60138945A/ja
Publication of JPH0714021B2 publication Critical patent/JPH0714021B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明０技術分１〕′ｉ この発明は、放熱フィン付の封止型半導体装　・：置に
関する。　１ 〔発明の技術的背景〕 従来、この種の樹脂封止型半導体装置は、例　“：えば
第１図あるいは第２図に示すよ′うな外観を　１＊Ｌ−
Ｃい６．、、。およ。２工おい７、　：１１は樹脂製の
外囲器、１２，１２．・・・は上記外囲器１ノに内蔵さ
れた半導体チップからの電極取り出し用のリードビン、
１３は放熱フィンである。第３図は、上記第２図に示し
た樹脂封止型半導体装置の外囲器１１を取シ除いて上方
から見た平面図を示している。上記リードビン１２．１
２．・・・のインナーリード部に１１、放熱フィン、１
３上に載設された半導体チッ７°１４の電極１１：４　
ａ　、　１４　ａ　、・・・がデンディングワイヤ１５
　、’１５　、・・・によって接続される。なお、１３
ａは放熱器の取付は穴である。第４図は、上記第３図に
おけるｘ　−ｘ’線に沿った断面構成を示し１ている。
図において、上記第３図と対応する部分に同、じ・符号
を付す。
上記・のような構成の樹脂封止型半導体装置における機
器への実装は、上記リードビン１２゜１２、・・・・を
プリント基板のスルーホールに挿入１−て半田付け、あ
るいはプリント基板に設けたソケＪ）に挿入することに
よって行なわれ、前記放熱フィン１３には放熱器が取付
けらｆ＋る。
Ｃ骨素技術の問題点〕 ところで近年、上述したような樹脂封止型半導体装置が
各種の機器に使用されるに至シ、各機器の小型軽量化、
薄型化への要求、およびコスト低減策としての自動化か
ら各ノクーツの平面実装化が望まねているが、放熱フィ
ン付きのものではこの平面実装化が困難である。また、
前記放熱フィン１３への放熱器の取付けは、前記放熱フ
ィン１３に設けた取付は穴１３ｍを用いてネジ止めによ
って行なわれるため、実装工程の完全な自動化が困難で
あシ、この点の改良も望まれている。
〔発明の目的〕
この発明は上記のような事情に鑑みてなされメξもので
、その目的とするところは、実装工程の完全な自動化に
よるコストダウンが可能でらシ、且つ平面実装化を実現
できるすぐれた封止型半導体装置を提供することである
。
〔発明の概要〕
すなわち、この発明においては、上記の目的音ｉ成する
ために、半導体ベレットを外囲器に封止し、上記半導体
ペレットの電極数シ出し用のリードピンを配線基板に半
田付けして平面実装する封止ｍ＃−導体装置において、
上記リードピンに対応した折曲構造の放熱フィンを設け
、この放熱フィンを放熱器構造を有する上記配線基板に
半田付けして装着するようにしたものである。
〔発明の実施例〕
以下、この発明の一実施例について図面を参照して説明
する。第５図において、前記第１図あるいは第２図と同
一部分に同じ符号を付す。
すなわち、放熱フィン１３をリードピン１２゜１２、・
・・に対応した構造に折曲形成したもので、この封止型
半導体装置の実装時には、プリント基板（配線基板）の
−？ンディング領域にリードピン１２　、１２　、・・
・を載置して半田付けするとともに、放熱フィン１３を
放熱器構造に形成した上記プリント基板に半田付けする
。上記放熱フィン１３の材質としては、例えばＣｕ、１
９４アロイ、４２７０イ等要求される特性に応じて選定
する。
このような構成によれば、放熱フィン１３への放熱器の
工（■り伺けをリードピン１２，１２゜・・・の半田付
は時に同時に行なえ、実装工程の完全な自動化による実
装効率の向上および低コスト化を実現できる。また、前
記第１図あるいは第２図に示した構成では困難であった
平面実装を可能にできる。さらに、放熱器の取υ付けが
□、。
半田伺りであるため、ネジ止めよりも外囲器　：１１に
対して低衝撃であり、熱的なストレスや、□。
寿命の向上も図れる。
な督、この発明は上記実施例に限定されるも、□のでは
すく、要旨を逸脱しない範囲で種々変形１１′ ［７，て実施が可能であり、例えば第６図に示すように
構成してもよい１３図において前記第５図と１同一部分
に同じ符号を付す。すなわち、前記−□ ５図においては、外囲器１１の両側に放熱フイ、：′ン
１３を設けたのに対し、放熱フィン１３を廿囲器１１の
一方側のみに設けたものである。このような構成におい
ても上記実施例と同様な効果が得られるのはもちろんで
ある。
また、上記実施例では外囲器１）が樹脂製のものの場合
について説明したが、セラミック等信の材質にも適用で
き、ＤＩＰ型の外囲器について説明したがＳＩＰ型等他
等信囲器であっても良い。
〔発明の効果〕
以上説明したようにこの発明によれば、実装工程の完全
な自動化によるコストダウンが可能であり、且つ平面実
装化を実現できるすぐれた封止型半導体装置が得られる
っ
【図面の簡単な説明】
第１図および第２図はそれぞれ従来の封止型半導体装置
の外観斜視図、第３図は上記第２図の封止型半導体装置
の外囲器を取シ除いて示す平面図、第４図は上記第３図
のｘ　−ｘ’線に沿った断面構成図、第５図はこの発明
の一実施例に係る封止型半導体装置の外観斜視図、第６
図はこの発明の他の実施例を示す外観斜視図である。 １ノ・・・外囲器、１２，１２．・・・・・・リードピ
ン、１３・・・放熱フィン、１４・・・半導体チップ。

Claims (1)

  1. 【特許請求の範囲】 半導体ペレットを外囲器に封止し、上記半導体４レツト
    の電極取り出し用のリードビンを配線基板に半田伺けし
    て平面実装する封止型半導　。 体装置において、上記リードビンに対応した折曲構造の
    放熱フィンを設け、この放熱フィンを　１放熱器構造を
    有する上記配線基板に半田付けし　：、Ｕ：：：二：、
    ＜構成したことを特徴と□する封ｌＬ：
JP58244557A 1983-12-27 1983-12-27 樹脂封止型半導体装置 Expired - Lifetime JPH0714021B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58244557A JPH0714021B2 (ja) 1983-12-27 1983-12-27 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58244557A JPH0714021B2 (ja) 1983-12-27 1983-12-27 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPS60138945A true JPS60138945A (ja) 1985-07-23
JPH0714021B2 JPH0714021B2 (ja) 1995-02-15

Family

ID=17120477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58244557A Expired - Lifetime JPH0714021B2 (ja) 1983-12-27 1983-12-27 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPH0714021B2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
KR20000051980A (ko) * 1999-01-28 2000-08-16 유-행 치아오 히트 슬러그를 갖는 리드 프레임
US6297074B1 (en) * 1990-07-11 2001-10-02 Hitachi, Ltd. Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107251A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Electronic part and its packaging construction
JPS5947750A (ja) * 1982-09-10 1984-03-17 Hitachi Ltd 面取付型半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107251A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Electronic part and its packaging construction
JPS5947750A (ja) * 1982-09-10 1984-03-17 Hitachi Ltd 面取付型半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297074B1 (en) * 1990-07-11 2001-10-02 Hitachi, Ltd. Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
KR20000051980A (ko) * 1999-01-28 2000-08-16 유-행 치아오 히트 슬러그를 갖는 리드 프레임

Also Published As

Publication number Publication date
JPH0714021B2 (ja) 1995-02-15

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