JPS614462U - multilayer printed wiring board - Google Patents
multilayer printed wiring boardInfo
- Publication number
- JPS614462U JPS614462U JP8776784U JP8776784U JPS614462U JP S614462 U JPS614462 U JP S614462U JP 8776784 U JP8776784 U JP 8776784U JP 8776784 U JP8776784 U JP 8776784U JP S614462 U JPS614462 U JP S614462U
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- multilayer printed
- conductor circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は、多層印刷配線板の断面図および分解
構造断面図、第３図Ａ， Ｂ， Ｃは従来の空気溜りの
除去工程を示す側断面図、第４図はボイド部分の部分断
面斜視図、第５−図は本考案の内層板の斜視図。
″１・・・・・・導電層、１ａ・・・・・・導体回路、
２・・・・・・絶縁基材、２ａ・・・・・・透孔、３・
・・・・・プリプレグ、４・・・・・・外層板、４・・
・・・・部分剥離した外層板、５・・・・・・内層板、
６・・・・・・空気、７・・・・・・上型、８・・・・
・・下型、１０・・・・・・多層板。Figures 1 and 2 are a sectional view and exploded structure sectional view of a multilayer printed wiring board, Figures 3A, B, and C are side sectional views showing the conventional air trap removal process, and Figure 4 is a void section. Figure 5 is a perspective view of the inner layer plate of the present invention. ``1... conductive layer, 1a... conductor circuit,
2...Insulating base material, 2a...Through hole, 3.
...Prepreg, 4... Outer layer board, 4...
... Partially peeled outer layer board, 5... Inner layer board,
6...Air, 7...Upper mold, 8...
...lower mold, 10...multilayer board.
Claims (1)
を避けた位置に１個以上の透孔を設けて外層基板をプリ
プレグ層を介して接続したことを特徴とする多層印刷配
線板。A multilayer printed wiring board characterized in that an inner layer insulating substrate having a conductor circuit provided on its surface is provided with one or more through holes at a position avoiding the conductor circuit, and an outer layer substrate is connected through a prepreg layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8776784U JPS614462U (en) | 1984-06-13 | 1984-06-13 | multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8776784U JPS614462U (en) | 1984-06-13 | 1984-06-13 | multilayer printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS614462U true JPS614462U (en) | 1986-01-11 |
Family
ID=30640287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8776784U Pending JPS614462U (en) | 1984-06-13 | 1984-06-13 | multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS614462U (en) |
-
1984
- 1984-06-13 JP JP8776784U patent/JPS614462U/en active Pending
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