JPS6141080B2 - - Google Patents
Info
- Publication number
- JPS6141080B2 JPS6141080B2 JP54020418A JP2041879A JPS6141080B2 JP S6141080 B2 JPS6141080 B2 JP S6141080B2 JP 54020418 A JP54020418 A JP 54020418A JP 2041879 A JP2041879 A JP 2041879A JP S6141080 B2 JPS6141080 B2 JP S6141080B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- information
- cell
- defective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 34
- 238000012360 testing method Methods 0.000 claims description 27
- 230000002950 deficient Effects 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 16
- 238000007689 inspection Methods 0.000 claims description 15
- 230000007547 defect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2041879A JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2041879A JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55113200A JPS55113200A (en) | 1980-09-01 |
| JPS6141080B2 true JPS6141080B2 (enrdf_load_stackoverflow) | 1986-09-12 |
Family
ID=12026478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2041879A Granted JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55113200A (enrdf_load_stackoverflow) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57164497A (en) * | 1981-03-31 | 1982-10-09 | Toshiba Corp | Controlling device of address fail memory |
| JPS6050698A (ja) * | 1983-08-26 | 1985-03-20 | Mitsubishi Electric Corp | 半導体試験装置 |
| JPS60106100A (ja) * | 1983-11-15 | 1985-06-11 | Fujitsu Ltd | 半導体メモリの試験方法 |
| EP0424612A3 (en) * | 1989-08-30 | 1992-03-11 | International Business Machines Corporation | Apparatus and method for real time data error capture and compression for redundancy analysis of a memory |
| JP2007172778A (ja) * | 2005-12-26 | 2007-07-05 | Nec Electronics Corp | メモリテスト回路及びメモリテスト方法 |
-
1979
- 1979-02-22 JP JP2041879A patent/JPS55113200A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55113200A (en) | 1980-09-01 |
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