JPS6139579A - 薄膜トランジスタマトリックスアレイの製造方法 - Google Patents

薄膜トランジスタマトリックスアレイの製造方法

Info

Publication number
JPS6139579A
JPS6139579A JP15868784A JP15868784A JPS6139579A JP S6139579 A JPS6139579 A JP S6139579A JP 15868784 A JP15868784 A JP 15868784A JP 15868784 A JP15868784 A JP 15868784A JP S6139579 A JPS6139579 A JP S6139579A
Authority
JP
Japan
Prior art keywords
tft
bus line
gate
drain
matrix array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15868784A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0586870B2 (enrdf_load_stackoverflow
Inventor
Yasuhiro Nasu
安宏 那須
Satoru Kawai
悟 川井
Kenichi Yanai
梁井　健一
Atsushi Inoue
淳 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15868784A priority Critical patent/JPS6139579A/ja
Publication of JPS6139579A publication Critical patent/JPS6139579A/ja
Publication of JPH0586870B2 publication Critical patent/JPH0586870B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP15868784A 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法 Granted JPS6139579A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15868784A JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15868784A JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Publications (2)

Publication Number Publication Date
JPS6139579A true JPS6139579A (ja) 1986-02-25
JPH0586870B2 JPH0586870B2 (enrdf_load_stackoverflow) 1993-12-14

Family

ID=15677157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15868784A Granted JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Country Status (1)

Country Link
JP (1) JPS6139579A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136571A (ja) * 1986-11-27 1988-06-08 Nec Corp 薄膜トランジスタアレイ
JPH02109341A (ja) * 1988-10-19 1990-04-23 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
JPH04111323A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法
JPH04111322A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58173847A (ja) * 1982-04-07 1983-10-12 Matsushita Electric Ind Co Ltd 素子作製方法
JPS5922030A (ja) * 1982-07-28 1984-02-04 Matsushita Electric Ind Co Ltd マトリクス表示パネルの製造方法
JPS5942584A (ja) * 1982-08-31 1984-03-09 シャープ株式会社 マトリツクス型液晶表示装置
JPS60261174A (ja) * 1984-06-07 1985-12-24 Nippon Soken Inc マトリツクスアレ−

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58173847A (ja) * 1982-04-07 1983-10-12 Matsushita Electric Ind Co Ltd 素子作製方法
JPS5922030A (ja) * 1982-07-28 1984-02-04 Matsushita Electric Ind Co Ltd マトリクス表示パネルの製造方法
JPS5942584A (ja) * 1982-08-31 1984-03-09 シャープ株式会社 マトリツクス型液晶表示装置
JPS60261174A (ja) * 1984-06-07 1985-12-24 Nippon Soken Inc マトリツクスアレ−

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136571A (ja) * 1986-11-27 1988-06-08 Nec Corp 薄膜トランジスタアレイ
JPH02109341A (ja) * 1988-10-19 1990-04-23 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
JPH04111323A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法
JPH04111322A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法

Also Published As

Publication number Publication date
JPH0586870B2 (enrdf_load_stackoverflow) 1993-12-14

Similar Documents

Publication Publication Date Title
US6927105B2 (en) Thin film transistor array substrate and manufacturing method thereof
US6562645B2 (en) Method of fabricating fringe field switching mode liquid crystal display
US20010035527A1 (en) Active matrix substrate and manufacturing method thereof
KR100975734B1 (ko) 횡전계방식 액정 표시 장치용 어레이 기판 및 그 제조 방법
JP2008107849A (ja) 液晶表示装置及びその製造方法
US4990460A (en) Fabrication method for thin film field effect transistor array suitable for liquid crystal display
JPH0580650B2 (enrdf_load_stackoverflow)
KR100848108B1 (ko) 액정 표시 장치, 그의 박막 트랜지스터 기판 및 그 제조방법
JPS6139579A (ja) 薄膜トランジスタマトリックスアレイの製造方法
KR100386458B1 (ko) 액정 표시 장치용 어레이 기판 및 그의 제조 방법
JP2661163B2 (ja) Ｔｆｔパネル
JPS60261174A (ja) マトリツクスアレ−
US7348197B2 (en) Liquid crystal display device and fabrication method thereof
KR100650400B1 (ko) 액정 표시 장치용 어레이 기판 및 그의 제조 방법
WO2012073942A1 (ja) 半導体装置およびその製造方法
JP3167817B2 (ja) アクティブマトリックス型液晶表示装置
JP3202342B2 (ja) アレイ基板の製造方法
KR101970550B1 (ko) 박막트랜지스터 기판 및 그 제조 방법
JPH02198430A (ja) 薄膜電界効果型トランジスタ素子アレイ
JPH0570825B2 (enrdf_load_stackoverflow)
KR100397672B1 (ko) 액정 표시 장치용 어레이 기판 및 그의 제조 방법
JPH0627981B2 (ja) アクテイブマトリツクス型表示装置用表示電極アレイとその製造方法
JPH04106938A (ja) 薄膜電界効果型トランジスタ
JPH04268536A (ja) アクティブマトリクス基板およびその製造方法
JPH01227127A (ja) 薄膜トランジスタアレイ

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term