JPS6130309B2 - - Google Patents

Info

Publication number
JPS6130309B2
JPS6130309B2 JP56039838A JP3983881A JPS6130309B2 JP S6130309 B2 JPS6130309 B2 JP S6130309B2 JP 56039838 A JP56039838 A JP 56039838A JP 3983881 A JP3983881 A JP 3983881A JP S6130309 B2 JPS6130309 B2 JP S6130309B2
Authority
JP
Japan
Prior art keywords
input
control
output
output device
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56039838A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57153364A (en
Inventor
Tsutomu Sakamaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56039838A priority Critical patent/JPS57153364A/ja
Publication of JPS57153364A publication Critical patent/JPS57153364A/ja
Publication of JPS6130309B2 publication Critical patent/JPS6130309B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
JP56039838A 1981-03-18 1981-03-18 Calculation controller Granted JPS57153364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56039838A JPS57153364A (en) 1981-03-18 1981-03-18 Calculation controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56039838A JPS57153364A (en) 1981-03-18 1981-03-18 Calculation controller

Publications (2)

Publication Number Publication Date
JPS57153364A JPS57153364A (en) 1982-09-21
JPS6130309B2 true JPS6130309B2 (en, 2012) 1986-07-12

Family

ID=12564097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56039838A Granted JPS57153364A (en) 1981-03-18 1981-03-18 Calculation controller

Country Status (1)

Country Link
JP (1) JPS57153364A (en, 2012)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63225848A (ja) * 1987-03-16 1988-09-20 Agency Of Ind Science & Technol 計算機システム

Also Published As

Publication number Publication date
JPS57153364A (en) 1982-09-21

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