JPS61296450A - キヤツシユメモリ制御方法 - Google Patents
キヤツシユメモリ制御方法Info
- Publication number
- JPS61296450A JPS61296450A JP60137680A JP13768085A JPS61296450A JP S61296450 A JPS61296450 A JP S61296450A JP 60137680 A JP60137680 A JP 60137680A JP 13768085 A JP13768085 A JP 13768085A JP S61296450 A JPS61296450 A JP S61296450A
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- cache memory
- address
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137680A JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137680A JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61296450A true JPS61296450A (ja) | 1986-12-27 |
| JPH0415495B2 JPH0415495B2 (cg-RX-API-DMAC7.html) | 1992-03-18 |
Family
ID=15204302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60137680A Granted JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61296450A (cg-RX-API-DMAC7.html) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482256A (en) * | 1987-09-25 | 1989-03-28 | Fujitsu Ltd | Vector data fetch system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59178671A (ja) * | 1983-03-29 | 1984-10-09 | Fujitsu Ltd | バツフアストレイジリプレイス方式 |
-
1985
- 1985-06-26 JP JP60137680A patent/JPS61296450A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59178671A (ja) * | 1983-03-29 | 1984-10-09 | Fujitsu Ltd | バツフアストレイジリプレイス方式 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482256A (en) * | 1987-09-25 | 1989-03-28 | Fujitsu Ltd | Vector data fetch system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0415495B2 (cg-RX-API-DMAC7.html) | 1992-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5091851A (en) | Fast multiple-word accesses from a multi-way set-associative cache memory | |
| US4466059A (en) | Method and apparatus for limiting data occupancy in a cache | |
| JPS6135584B2 (cg-RX-API-DMAC7.html) | ||
| JPS61156346A (ja) | 記憶階層の先取り装置 | |
| JPS5876956A (ja) | バッファ記憶付きディスク・システム | |
| JP3236287B2 (ja) | マルチプロセッサシステム | |
| US8621152B1 (en) | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | |
| EP0533427B1 (en) | Computer memory control system | |
| US5287512A (en) | Computer memory system and method for cleaning data elements | |
| JPH044617B2 (cg-RX-API-DMAC7.html) | ||
| JP2002140232A (ja) | マルチプロセッサシステム及びキャッシュを制御する方法 | |
| JPS61296450A (ja) | キヤツシユメモリ制御方法 | |
| JPH0290259A (ja) | マルチプロセッサシステム | |
| JPS644214B2 (cg-RX-API-DMAC7.html) | ||
| JPH02213960A (ja) | キャッシュメモリ | |
| JP2963257B2 (ja) | 処理装置 | |
| KR100546295B1 (ko) | 데이타 전송 시간을 줄인 2-레벨 캐쉬 메모리 시스템 | |
| JP2637853B2 (ja) | キャッシュメモリ装置 | |
| JPS61235960A (ja) | キヤツシユメモリの制御方法 | |
| JPS62145341A (ja) | キヤツシユメモリシステム | |
| JPH0573415A (ja) | 階層化キヤツシユ方式 | |
| JPH0793215A (ja) | 半導体記憶装置 | |
| JPH04288647A (ja) | キャッシュメモリにおける置き換え制御装置 | |
| JPH05120139A (ja) | キヤツシユメモリ装置 | |
| EP0400851A2 (en) | Efficient cache utilizing a store buffer |