JPH0415495B2 - - Google Patents
Info
- Publication number
- JPH0415495B2 JPH0415495B2 JP60137680A JP13768085A JPH0415495B2 JP H0415495 B2 JPH0415495 B2 JP H0415495B2 JP 60137680 A JP60137680 A JP 60137680A JP 13768085 A JP13768085 A JP 13768085A JP H0415495 B2 JPH0415495 B2 JP H0415495B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- cache
- address
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137680A JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60137680A JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61296450A JPS61296450A (ja) | 1986-12-27 |
| JPH0415495B2 true JPH0415495B2 (cg-RX-API-DMAC7.html) | 1992-03-18 |
Family
ID=15204302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60137680A Granted JPS61296450A (ja) | 1985-06-26 | 1985-06-26 | キヤツシユメモリ制御方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61296450A (cg-RX-API-DMAC7.html) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482256A (en) * | 1987-09-25 | 1989-03-28 | Fujitsu Ltd | Vector data fetch system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59178671A (ja) * | 1983-03-29 | 1984-10-09 | Fujitsu Ltd | バツフアストレイジリプレイス方式 |
-
1985
- 1985-06-26 JP JP60137680A patent/JPS61296450A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61296450A (ja) | 1986-12-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5537572A (en) | Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM) | |
| US5091851A (en) | Fast multiple-word accesses from a multi-way set-associative cache memory | |
| EP0077453B1 (en) | Storage subsystems with arrangements for limiting data occupancy in caches thereof | |
| US5249284A (en) | Method and system for maintaining data coherency between main and cache memories | |
| CN101593161A (zh) | 确保微处理器的快取存储器层级数据一致性的装置与方法 | |
| JPH06208508A (ja) | キャッシュタグメモリ | |
| US8621152B1 (en) | Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access | |
| JP3236287B2 (ja) | マルチプロセッサシステム | |
| EP0533427B1 (en) | Computer memory control system | |
| US5287512A (en) | Computer memory system and method for cleaning data elements | |
| US6240487B1 (en) | Integrated cache buffers | |
| JP2002140232A (ja) | マルチプロセッサシステム及びキャッシュを制御する方法 | |
| JPH044617B2 (cg-RX-API-DMAC7.html) | ||
| KR20240055651A (ko) | 듀얼 인터페이스를 포함하는 영구 스토리지 | |
| JPH0415495B2 (cg-RX-API-DMAC7.html) | ||
| JPH05282208A (ja) | キャッシュメモリ制御方式 | |
| JPH0290259A (ja) | マルチプロセッサシステム | |
| JPH02213960A (ja) | キャッシュメモリ | |
| KR20040047398A (ko) | 캐쉬 메모리를 이용한 데이터 억세스 방법 | |
| JP2850340B2 (ja) | キャッシュメモリ制御回路 | |
| JP2963257B2 (ja) | 処理装置 | |
| JPH08137753A (ja) | ディスクキャッシュ装置 | |
| JPS6020255A (ja) | バツフア記憶制御方式 | |
| JPH06222989A (ja) | コピーバックキャッシュタグメモリ | |
| JPH07152650A (ja) | キャッシュ制御装置 |