JPS6482256A - Vector data fetch system - Google Patents

Vector data fetch system

Info

Publication number
JPS6482256A
JPS6482256A JP62241723A JP24172387A JPS6482256A JP S6482256 A JPS6482256 A JP S6482256A JP 62241723 A JP62241723 A JP 62241723A JP 24172387 A JP24172387 A JP 24172387A JP S6482256 A JPS6482256 A JP S6482256A
Authority
JP
Japan
Prior art keywords
vector data
lbs
replacement
pertinent
priority level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62241723A
Other languages
Japanese (ja)
Inventor
Hideaki Fujimaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62241723A priority Critical patent/JPS6482256A/en
Publication of JPS6482256A publication Critical patent/JPS6482256A/en
Pending legal-status Critical Current

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  • Complex Calculations (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To improve the hit rate of vector data by using a mechanism, which sets the priority level of replacement for moving-in to a local buffer storage to the lowest level, to fetch vector data. CONSTITUTION:When it is recognized in an IPU 10 that a vector instruction is set to an instruction buffer, a flag F 17 indicating that it accesses vector data is turned on and is sent to a storage control unit SCU 11. The SCU 11 sees the flag signal to recognize that this signal is turned on, and the priority level of replacement to pertinent vector data in an LRU mechanism 111 of an operand LBS 110b is set to the lowest level. That is, the priority level of replacement to the storage position of a vector data block at the time of moving-in is always set to the lowest level in a pertinent address. By this control, destruction of data for a general machine is prevented to reduce the degradation in hit rate of a pertinent LBS 110 for the general machine at the time of prefetching the operand LBS 110b of vector data.
JP62241723A 1987-09-25 1987-09-25 Vector data fetch system Pending JPS6482256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62241723A JPS6482256A (en) 1987-09-25 1987-09-25 Vector data fetch system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62241723A JPS6482256A (en) 1987-09-25 1987-09-25 Vector data fetch system

Publications (1)

Publication Number Publication Date
JPS6482256A true JPS6482256A (en) 1989-03-28

Family

ID=17078578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62241723A Pending JPS6482256A (en) 1987-09-25 1987-09-25 Vector data fetch system

Country Status (1)

Country Link
JP (1) JPS6482256A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296450A (en) * 1985-06-26 1986-12-27 Hitachi Ltd Cache memory control method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296450A (en) * 1985-06-26 1986-12-27 Hitachi Ltd Cache memory control method

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