JPS6488757A - Data cache control system - Google Patents

Data cache control system

Info

Publication number
JPS6488757A
JPS6488757A JP62246130A JP24613087A JPS6488757A JP S6488757 A JPS6488757 A JP S6488757A JP 62246130 A JP62246130 A JP 62246130A JP 24613087 A JP24613087 A JP 24613087A JP S6488757 A JPS6488757 A JP S6488757A
Authority
JP
Japan
Prior art keywords
data
local
cache
data cache
writing action
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62246130A
Other languages
Japanese (ja)
Other versions
JP2573255B2 (en
Inventor
Teruhisa Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62246130A priority Critical patent/JP2573255B2/en
Priority to KR1019880012817A priority patent/KR890005619A/en
Publication of JPS6488757A publication Critical patent/JPS6488757A/en
Priority to US08/401,292 priority patent/US5513353A/en
Application granted granted Critical
Publication of JP2573255B2 publication Critical patent/JP2573255B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize a high-speed data cache control system by changing the data on a data cache only and inhibiting the writing action of a main memory in case the writing action of the local data received from a CPU has a hit in the data cache. CONSTITUTION:When a micro-CPU 1 writes data, the write-through processing, etc., are applied to the global data and only the data on a data field 38 is changed for the local data in case of having a hit with no writing action applied to a main memory 2. When the muCPU 1 carries out an instruction to cancel a local area against a stack, a G/L flag 35 of a data cache 3 where the present task number is coincident with a task number 36 is set at G (global). A present flag 39 of the local area of the cache 3 is set when a writing action is applied to the local area and then produces a trap to inform an abnormal access in case the CPU 1 reads the local data while no flag 39 is set. Thus the access speed is improved to the local data.
JP62246130A 1987-09-30 1987-09-30 Data cache control method Expired - Lifetime JP2573255B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62246130A JP2573255B2 (en) 1987-09-30 1987-09-30 Data cache control method
KR1019880012817A KR890005619A (en) 1987-09-30 1988-09-30 Data Cache Memory Control System in Data Processing Equipment
US08/401,292 US5513353A (en) 1987-09-30 1995-03-09 Cache control system which permanently inhibits local but not global parameter data writes to main memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246130A JP2573255B2 (en) 1987-09-30 1987-09-30 Data cache control method

Publications (2)

Publication Number Publication Date
JPS6488757A true JPS6488757A (en) 1989-04-03
JP2573255B2 JP2573255B2 (en) 1997-01-22

Family

ID=17143925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246130A Expired - Lifetime JP2573255B2 (en) 1987-09-30 1987-09-30 Data cache control method

Country Status (2)

Country Link
JP (1) JP2573255B2 (en)
KR (1) KR890005619A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242003A (en) * 2006-02-07 2007-09-20 Intel Corp Technique for using memory attributes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142437A (en) * 1982-02-18 1983-08-24 Toshiba Corp Information processor
JPS6079446A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Processor for multiple virtual storage data

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142437A (en) * 1982-02-18 1983-08-24 Toshiba Corp Information processor
JPS6079446A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Processor for multiple virtual storage data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242003A (en) * 2006-02-07 2007-09-20 Intel Corp Technique for using memory attributes

Also Published As

Publication number Publication date
KR890005619A (en) 1989-05-16
JP2573255B2 (en) 1997-01-22

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