JPS648454A - Control area monitoring system for virtual computer system - Google Patents

Control area monitoring system for virtual computer system

Info

Publication number
JPS648454A
JPS648454A JP62162324A JP16232487A JPS648454A JP S648454 A JPS648454 A JP S648454A JP 62162324 A JP62162324 A JP 62162324A JP 16232487 A JP16232487 A JP 16232487A JP S648454 A JPS648454 A JP S648454A
Authority
JP
Japan
Prior art keywords
register
control area
value
virtual computer
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162324A
Other languages
Japanese (ja)
Inventor
Seiji Kaneko
Shinya Watabe
Hidenori Umeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62162324A priority Critical patent/JPS648454A/en
Publication of JPS648454A publication Critical patent/JPS648454A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To reduce or omit the number of times of inspection and overhead in a control area of a main memory and to immediately transmit a control area changing event to an operating virtual computer by forming a mechanism for monitoring a control area of the virtual computer independently of a processor. CONSTITUTION:The titled system is constituted of a register 112 for holding the addresses of the main memory to monitor an updating mechanism 11, a register 111 for holding copies, an AND part 114 for finding out AND operation between the value of the register 111 and an output from a PSW 121 for holding a current I/O mask and generating a break-in request to a processor interruption control part 12 in accordance with the AND value, and a control part including a period timer 113. The timer 113 starts the mechanism 11 at a certain fixed period, reads out an address indicated by the register 112 and writes data in the register 111. When a value is written in the register 111 or the value of the PSW 121 is changed, their AND is immediately formed by the AND gate 114, a break-in request is generated and interception processing is started by the control part 12.
JP62162324A 1987-07-01 1987-07-01 Control area monitoring system for virtual computer system Pending JPS648454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162324A JPS648454A (en) 1987-07-01 1987-07-01 Control area monitoring system for virtual computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162324A JPS648454A (en) 1987-07-01 1987-07-01 Control area monitoring system for virtual computer system

Publications (1)

Publication Number Publication Date
JPS648454A true JPS648454A (en) 1989-01-12

Family

ID=15752370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162324A Pending JPS648454A (en) 1987-07-01 1987-07-01 Control area monitoring system for virtual computer system

Country Status (1)

Country Link
JP (1) JPS648454A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230533A (en) * 1990-11-02 1993-07-27 Nsk Ltd. Shock absorbing steering apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230533A (en) * 1990-11-02 1993-07-27 Nsk Ltd. Shock absorbing steering apparatus

Similar Documents

Publication Publication Date Title
EP0496506A3 (en) A processing unit for a computer and a computer system incorporating such a processing unit
SE9101325L (en) PROCEDURE TO INCREASE DATA PROCESSING RATE IN COMPUTER SYSTEM
ES8702011A1 (en) Address translation control system.
JPS5492137A (en) Buffer setting system
DE3069674D1 (en) Data processing system including internal register addressing arrangements
JPS648454A (en) Control area monitoring system for virtual computer system
JPS5475964A (en) Data pre-fetch system
JPS57152065A (en) Programmable logic controller
JPS5619153A (en) Virtual computer system
JPH04306750A (en) Multiprocessor system
JPH01128156A (en) Cache control system for multi-processor system
JPS6488757A (en) Data cache control system
JPH0458347A (en) Control system for shared address space
JPS6482240A (en) Information processing system
DE59208202D1 (en) PROGRAMMABLE CONTROL
JPH0588980A (en) Multiprocessor system
JPS5447531A (en) Memory control system for multi-processor system possessing intermediate buffer memory
JPS54146927A (en) Display system of data input device
JPS55128946A (en) Data transfer control circuit
JPS6473450A (en) Spatial arrangement control method
JPH04163646A (en) Cache updating error processing system
JPS5712469A (en) Buffer memory control system
JPH0462649A (en) Fetch control system for instruction data to instruction cache
JPH0371250A (en) Partial cache controller
JPS5613575A (en) Memory system