JPS61294562A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JPS61294562A
JPS61294562A JP60136539A JP13653985A JPS61294562A JP S61294562 A JPS61294562 A JP S61294562A JP 60136539 A JP60136539 A JP 60136539A JP 13653985 A JP13653985 A JP 13653985A JP S61294562 A JPS61294562 A JP S61294562A
Authority
JP
Japan
Prior art keywords
address
signal
memory cell
data
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60136539A
Other languages
English (en)
Japanese (ja)
Inventor
Tatsuo Yamada
山田　達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60136539A priority Critical patent/JPS61294562A/ja
Priority to US06/854,639 priority patent/US4763302A/en
Priority to DE19863618136 priority patent/DE3618136A1/de
Publication of JPS61294562A publication Critical patent/JPS61294562A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
JP60136539A 1985-06-21 1985-06-21 半導体記憶装置 Pending JPS61294562A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60136539A JPS61294562A (ja) 1985-06-21 1985-06-21 半導体記憶装置
US06/854,639 US4763302A (en) 1985-06-21 1986-04-22 Alternatively addressed semiconductor memory array
DE19863618136 DE3618136A1 (de) 1985-06-21 1986-05-30 Abwechselnd adressierte halbleiterspeichergruppe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60136539A JPS61294562A (ja) 1985-06-21 1985-06-21 半導体記憶装置

Publications (1)

Publication Number Publication Date
JPS61294562A true JPS61294562A (ja) 1986-12-25

Family

ID=15177554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60136539A Pending JPS61294562A (ja) 1985-06-21 1985-06-21 半導体記憶装置

Country Status (3)

Country Link
US (1) US4763302A (en, 2012)
JP (1) JPS61294562A (en, 2012)
DE (1) DE3618136A1 (en, 2012)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257234A (en) * 1987-07-15 1993-10-26 Hitachi, Ltd. Semiconductor integrated circuit device
DE3884492T2 (de) * 1987-07-15 1994-02-17 Hitachi Ltd Integrierte Halbleiterschaltungsanordnung.
US4942319A (en) * 1989-01-19 1990-07-17 National Semiconductor Corp. Multiple page programmable logic architecture
US5021689A (en) * 1989-01-19 1991-06-04 National Semiconductor Corp. Multiple page programmable logic architecture
US5261073A (en) * 1989-05-05 1993-11-09 Wang Laboratories, Inc. Method and apparatus for providing memory system status signals
US6564308B2 (en) 1989-05-05 2003-05-13 Samsung Electronics Co. Ltd. Multiple mode memory module
US5307469A (en) * 1989-05-05 1994-04-26 Wang Laboratories, Inc. Multiple mode memory module
US5247655A (en) * 1989-11-07 1993-09-21 Chips And Technologies, Inc. Sleep mode refresh apparatus
US4985871A (en) * 1989-11-13 1991-01-15 Chips And Technologies, Inc. Memory controller for using reserved dram addresses for expanded memory space
US4999815A (en) * 1990-02-13 1991-03-12 International Business Machines Corporation Low power addressing systems
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
JP2900523B2 (ja) * 1990-05-31 1999-06-02 日本電気株式会社 不揮発性半導体メモリ装置の書込回路
JPH0676559A (ja) * 1992-06-26 1994-03-18 Mitsubishi Electric Corp ファーストインファーストアウトメモリ装置
US5526503A (en) * 1993-10-06 1996-06-11 Ast Research, Inc. Virtual addressing buffer circuit
US5532947A (en) * 1995-01-25 1996-07-02 International Business Machines Corporation Combined decoder/adder circuit which provides improved access speed to a cache
JP3807745B2 (ja) * 1995-06-14 2006-08-09 株式会社ルネサステクノロジ 半導体メモリ、メモリデバイス及びメモリカード
US6154825A (en) * 1997-03-07 2000-11-28 Intel Corporation Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations
KR100281900B1 (ko) * 1998-09-08 2001-02-15 윤종용 개선된 웨이퍼 번인 테스트 스킴을 갖는 반도체 메모리장치
TW516118B (en) * 2001-09-11 2003-01-01 Leadtek Research Inc Decoding conversion device and method capable of supporting multiple memory chips and their application system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800289A (en) * 1972-05-15 1974-03-26 Goodyear Aerospace Corp Multi-dimensional access solid state memory
CH613540A5 (en, 2012) * 1975-02-26 1979-09-28 Siemens Ag
DE2942741A1 (de) * 1979-10-23 1981-05-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Anordnung fuer einen speicher mit wahlfreiem zugriff
US4494222A (en) * 1980-03-28 1985-01-15 Texas Instruments Incorporated Processor system using on-chip refresh address generator for dynamic memory
JPS573289A (en) * 1980-06-04 1982-01-08 Hitachi Ltd Semiconductor storing circuit device
JPS60200287A (ja) * 1984-03-24 1985-10-09 株式会社東芝 記憶装置

Also Published As

Publication number Publication date
US4763302A (en) 1988-08-09
DE3618136C2 (en, 2012) 1992-02-13
DE3618136A1 (de) 1987-01-02

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