JPS6126476A - Control circuit for inverter - Google Patents

Abstract

PURPOSE:To obtain a signal of an inverter frequency for an object with a simple configuration by varying the output period of a switching signal pattern of an inverter stored in a ROM by varying the system clock of a microcomputer. CONSTITUTION:A microcomputer 7 inputs as input data inverter frequency command data 12, an address signal is applied to a ROM11 in response to the inverter frequency command, and a switching signal pattern is output from the ROM11. A rate multiplier 9 varies the frequency of the oscillation output form an oscillator 10 in response to the frequency command data, the output of the multiplier 9 is divided in frequency by 1/n frequency divider 8, and input to the microcomputer 7 as a clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a control circuit for an inverter device that controls the speed of an AC motor.

Conventional Structure and Problems The structure of a conventional inverter control circuit is shown in FIGS. 1 to 3. In Figure 1, 1 is a one-chip microcomputer (hereinafter abbreviated as microcomputer), and 2 is a read-only microcomputer.
Memory (hereinafter abbreviated as ROM) 3 is an oscillator, 4 is inverter frequency reference data, and 5 is a switching signal output to the transistor inverter. Figure 2 is a circuit diagram of a transistor inverter assembled into a three-phase bridge.
6 transistors 01 to Q6 and 6 diodes D
1 to D6, and a base amplification circuit 6 of transistors Q1 to Q6.

Before explaining the operation of the conventional structure, the data structure of the ROM 2 will be explained. ROM 2 generally contains:
4096 words x 8 bits or 8192 words x 8 bits are used to store switching signal pattern data that drives the base amplifier circuit 6 of transistors 01 to Q6. , switching signal pattern data is prepared. The data of this switching signal pattern is
For each inverter frequency, one period (0 degrees to 360 degrees of phase angle) is stored, and the three-phase transistor inverter is controlled by repeatedly outputting that one period of data. It is supposed to be done.

An example of the data structure of the ROM 2 is shown in FIG.

In this example, the inverter frequency F. The data of the switching signal pattern in this case is the address oo of ROM2.
ooH (II (J at the end indicates hexadecimal).

Similarly, data for inverter frequency F1 is stored in 1024 words from address 0400H to 07FFH in ROM2, and data for inverter frequency F2 is stored in 1024 words from address 0400H to 07FFH in ROM2. Address, osooH to oBFFH
Data is stored in the 1024 words up to... Here, one word of ROM2 consists of 8 bits of Do-Dy as shown in FIG. 3, but since it is only necessary to control the six transistors Q1 to Q6 in FIG. Only 6 bits out of 8 bits per word need to be used as data. As for the remaining two bits, it is sufficient to input appropriate data and leave them idle. In the example in Figure 3, the beep) Do-
The 6 bits of Des correspond to the switching signals of transistors Q1 to Q6, so that data "1" turns the transistor "ON" and data "0" turns the transistor 1'.
-0FFJ is supported. Also, beep)D6゜D7
The two bits are allowed to play.

Next, the operation of the conventional configuration will be described based on FIGS. 1 to 3. In the configuration example of ROM2 shown in Fig. 3, the switching signal pattern data for one inverter frequency consists of 1o24 words x 6 bits, which are output in the order of addresses to obtain the inverter switching signal. ing. For example, if the inverter frequency is F. If you proceed with o3FFHi, then return to 0OOOH and address in order again, repeating this.
The switching signal data of the inverter frequency F0 stored in 7)"l/s0OOOH to 03FFH of ROM2 is obtained. Therefore, the switching signal data of the inverter frequency F0 stored in 7)"l/s0OOOH of ROM2 is obtained.
The time for addressing 1024 words from 000H to 03FFH must match the period of the inverter frequency F0. Other inverter frequencies F1. F2.
0. , -9. The same applies to these other inverter frequencies F1. F2. ... is also F. Similarly, one cycle of data consists of 1024 words.

However, the time to address those 1o24 words is
They are all different because they have to match the period of the inverter frequency. Here, the following first equation holds between the timing period T (sec) for changing the address of the ROM 2 and the inverter frequency F (Hz).

F=1/(1024XT) -=-(*) As mentioned above, it is the microcomputer 1 that addresses the ROM2, but this microcomputer 1 takes in the inverter frequency command data 4, and then inputs the inverter frequency command data 4. Frequency command data 4
ROM2 is addressed in the manner described above. For example, if the inverter frequency command data 4 specifies the inverter frequency F0, the microcomputer 1
2, sequentially address from 0OOOH to 03FFH and repeat this.

The output of the oscillator 3 is applied to the clock terminal of the microcomputer 1 to generate the microcomputer's system clock, which has a certain frequency. That is, the machine cycle of the microcomputer is a constant value determined by the oscillator 3.

As mentioned above, in order to change the address time of 1024 words of ROM2 according to the inverter frequency when the inverter frequency command data 4 changes, the first equation is used.
The timing period T for changing the address must be changed, but since the microcomputer's machine cycle is a constant value, in order to change the timing period T, a timer must be configured in the microcomputer's software.

In other words, the minimum width of the timing period T for changing the address is the main cycle of the microcomputer 1. In addition to the fact that even a high-speed 4-bit one-chip microcontroller used for consumer use generally has a machine cycle of about 1 (μsec), this also explains the following. It is the cause of defects.

Now, let us consider the data structure of ROM2 as shown in Figure 3. Assuming that the machine cycle of microcomputer 1 is tm (sec) and the address change timing period is Tn (sec) when the inverter frequency is Fn (Hz), the minimum control width ΔFn when the inverter frequency is Fn is given by the first equation. It is expressed by the following equation.

ΔFn−hekiF. In the second equation, the machine cycle tm of the microcomputer 1 is tm==1, assuming that it is normally applied to a home air conditioner, etc.
(μ5ec), inverter frequency Fn = 30Hz,
60Hz, 10QHzty), respectively, the minimum control width ΔFn of the inverter frequency is set to the second
When calculated according to the formula, it becomes as follows.

, JF n (F n = 30Hz) = 0.95Hz
・・・・・・(3) JF (F = 60Hz) =
3.93Hz ・-・-(4) n ΔFn (Fn=1oOH2)=11.41H2...
...(5) As can be seen from Equations 3 to 6, when the inverter frequency is low, the frequency can be finely controlled, but when the inverter frequency becomes high and reaches 100Hz, the minimum control width of the inverter frequency becomes 1oHz or more. turn into.

As described above, in the conventional configuration, the width of the minimum inverter frequency that can be controlled varies depending on the inverter frequency, and the higher the inverter frequency, the coarser the control frequency width, which is impractical. There is.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned conventional drawbacks and provides a practical inverter control circuit with a simple configuration.

Structure of the Invention The present invention varies the system clock of a microcomputer according to inverter frequency command data, and uses a ROB/I in which inverter switching signal data is stored in advance to vary the system clock. By addressing with a microcontroller that can
A device that varies the output cycle of the inverter's switching signal data to obtain a signal at the target inverter frequency, and the control width of the inverter frequency is constant over the entire variable frequency range and has a frequency width that does not cause any practical problems. It is.

DESCRIPTION OF THE EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. 4 and 6. FIG. 4 is a block diagram of one embodiment. As shown in this figure, an oscillator 1 that oscillates at a certain frequency
0 and its oscillation output as the input frequency, and a rate multiplier 9 that uses the 6-bit data of the inverter frequency command data 12 as the rate input, and a frequency divider that divides the output frequency of the rate multiplier 9 by 1/n. 8, a microcomputer 7 which receives the output of the branching device 8 as a clock input and the inverter frequency command data 12 as an input, and an RO having the same data structure as the conventional example shown in FIG.
It is composed of M11.

The relationship between the input frequency flN and the output frequency fOUT of the rate multiplier 9 is given by the following equation.

fOU T-M-fI H/64,
, , , , (6) Here, the variable M is the rate input of the rate multiplier 9, that is, the frequency command data 12
It takes an integer value from 0 to 63 depending on the state of the 6 bits. Now, if we call the 6 bits of this frequency command data (rate input data) 8, B, C, D, E, and F, respectively, the value of the variable M will be as shown in FIG.

Since the oscillation frequency of the oscillator 10 is constant, the input frequency fIN of the rate multiplier 9 is also constant, and according to equation 6, the variable M and the output frequency f of the rate multiplier are
It can be seen that OUT is in a proportional relationship. Also, the output frequency of the rate multiplier is fOUT, which is 1 by the frequency divider 8.
The frequency is divided by /n and given as a clock to the microcomputer 7. Therefore, the clock of the microcomputer 7 is also proportional to the variable M.

On the other hand, the microcomputer 7 outputs inverter frequency command data 12
The operation of taking in as input data, giving an address signal to RoMll according to the inverter frequency, and RoMll outputting a switching signal pattern is the same as in the conventional example, but in the embodiment according to the present invention, As mentioned above, the difference from the conventional method is that the clock of the microcomputer 7 is changed according to the inverter frequency command data.

Therefore, when the microcomputer 7 sends an address signal to the RoMll, there is no need to change the address change timing using the method described in the conventional example (a method of configuring a timer using microcomputer software); in this embodiment, By changing the clock of the microcomputer 7 and proportionally changing the machine cycle of the microcomputer 7 generated by this clock, the necessary address change timing is created, and the ROM 11 is repeatedly updated to the address at the desired inverter frequency. can do. In other words, the timing at which the microcomputer 7 changes the address depends on the machine of the microcomputer 7.
It depends only on the cycle.

The inverter frequency F is the clock frequency f of the microcomputer 7
. It is also proportional to the variable M of the rate multiplier 9. These relationships are as follows: % Formula % Inverter frequency command data 12-6
If we give meaning to the Pinoto data so that the variable M and the inverter frequency are in a proportional relationship in FIG. , the clock of the microcomputer 7 automatically adjusts the clock frequency according to the inverter frequency and the timing of changing the address by repeatedly addressing a predetermined range.
From formula 7, the minimum control width ΔF of the inverter frequency in this embodiment is as follows: ΔF=FMAX/63
・(8) becomes. However, FMAX is the highest required inverter frequency.

As can be seen from Equation 8, even if the inverter frequency changes, the minimum control width ΔF remains constant, and in the case of an inverter used in home air conditioners, FMAX " 1
Since it is about 20 H2, the minimum control width ΔF = 2
It becomes a little less than Hz, and it becomes possible to reach a level that poses no problem in practical use.

FIG. 5 shows another Song embodiment of the present invention, in which numeral 14 is a microcomputer with a built-in ROM, which combines the functions of the microcomputer 7 and ROM 11 in FIG. The rest is exactly the same as FIG. 4. In this case, it is more advantageous than the case shown in FIG. 4 in terms of reduced number of parts, reliability, and cost.

Effects of the Invention As described above, the present invention has a very simple configuration, and exhibits practical effects such as making it possible to keep the minimum variable width constant and small to the extent that there is no problem in practical use in the entire variable frequency range. It is something to do.

[Brief explanation of drawings]

Figure 1 is a block diagram of the conventional configuration, Figure 2 is a circuit diagram of the same three-phase transistor inverter, and Figure 3 is:
A diagram showing an example of the data structure of the ROM in the conventional example and the embodiment according to the present invention. FIG. 4 is a block diagram of the embodiment according to the present invention. FIG. 5 is a block diagram of the embodiment according to the present invention. FIG. 7"°°°... Microcomputer, 8... Frequency divider, 9.
... Rate multiplier, 10 ... Oscillator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] By varying the microcomputer system clock according to the inverter frequency command data,
An inverter control circuit that obtains a signal at a target inverter frequency by changing the output cycle of an inverter switching signal pattern that is stored in a read-only memory (ROM) in advance.