JPS59114486A - Sound amount variable circuit - Google Patents

Abstract

PURPOSE:To attenuate a sound amount, by changing the duty ratio of a high frequency signal piled up to an audible frequency signal with the elapse of time. CONSTITUTION:To a clock consisting of a reference signal generator 2, a frequency dividing circuit 4, a wave form shaping circuit 6, a drive circuit 8 and a motor 10, an alarm circuit 12 for outputting an H-level signal simultaneously with the arrival of set time, an audible sound generating circuit 14 for generating an audible signal on the basis of the signal from the frequency dividing circuit 4, a duty ratio variable circuit 18 for making the duty ratio of the high frequency signal from the frequency dividing circuit 4 variable and a duty ratio setting circuit 30 are provided. The duty ratio setting circuit 30 is equipped with an address counter 42 for counting the timing from a timing signal generating circuit 44 and the data of ROM40 corresponding to the counted value is sent to the duty ratio variable circuit 18. The duty ratio variable circuit 18 is equipped with an up-down counter 20 wherein an up-count period and a down-count period are changed corresponding to the data from ROM40.

Description

[Detailed Description of the Invention] The present invention relates to a volume variable mechanism for a circuit that generates a sound whose volume gradually changes over time, such as a melody or ticking sound. A variable volume circuit that can be built into an integrated circuit without any need and can be used for any waveform? This is what we are trying to provide.

2. Description of the Related Art Circuits that electronically create melodies, ticking sounds, etc. without using mechanical structures have been known.

In these circuits, in order to make the generated melody sounds and ticking sounds closer to natural sounds, a so-called envelope effect is added, which gradually attenuates the volume of each l note over time. Conventional methods for creating volume variations such as envelope effects include the use of charging/discharging waveforms using resistors and capacitors, or by sequentially turning on multiple transistors with different on-resistances and gradually varying the resistance value. There are known ways to obtain it.

However, the former tends to require resistors and capacitors to be externally attached to the integrated circuit, which poses a problem in terms of cost, and the latter requires that a large number of transistors with slightly different on-resistances be built into an integrated circuit. There were problems such as a decrease in yield due to the increase in size or the difficulty of adjusting the on-resistance value.Therefore, in recent years, the duty ratio of the waveforms that make up the melody, time beats, etc. has been gradually varied. A method completely different from the conventional method was proposed, and it was thought that this method would solve the above problems.

However, this method is effective only for square waves, and in recent years, the waveforms of melodies and beat sounds have been modified to become more complex in order to make them more similar to natural sounds. method could not be used.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a volume variable circuit that can be easily incorporated into an integrated circuit and can respond to any waveform of sound. be.

In order to achieve the above object, the present invention superimposes a high frequency signal having a frequency exceeding an audible frequency on an audible frequency signal such as a melody or ticking sound, and varies the duty ratio of the high frequency signal over time. Does the volume gradually decrease over time? Features.

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing a second embodiment of the present invention. In this embodiment, the present invention is applied to an alarm sound generation circuit for a clock to notify that a set time has arrived.

In the figure, a reference signal generator 21, a frequency divider circuit 4, a waveform shaping circuit 6. Drive circuit 8. A normal analog display clock is shown by the motor 10. The reference circuit 12 is a circuit that outputs an "H" signal at the same time as the set time arrives, and the audible sound generation circuit 14 outputs an "H" signal based on the signal from the frequency dividing circuit 4 when the signal of the reference circuit 12 becomes rHJ. In a circuit that generates an audible sound signal, the output signal is input to a gate circuit 16.

Further, the frequency dividing circuit 4 outputs a high frequency signal (IMHz in this embodiment) exceeding the audible frequency 9, and this signal is input to a variable duty ratio circuit 18 for varying the duty ratio. This variable duty ratio circuit 18 includes an up/down counter 20 . It includes a flip-flop (hereinafter abbreviated as FF) 22 and an inverter 24, and the above-mentioned high frequency signal is input to the clock signal φ of the up/down counter 20. The output of the reference circuit 12 via the inverter 28 is input to the manual reset method of the up/down counter 20, and when "H" is input, the up counter is reset to "L".
” becomes a down counter. The Q output of the FF 22 is input to the up/down switching force D. Further, the carry output of the amplifier down counter 20 via the inverter 24 is input to the preset enable input PE, and the output from the duty ratio selection circuit 30 is input to the preset inputs P1 to P5. Further, the carry output of the up/down counter 20 is inputted to the clock input φ of the FF 22 via the inverter 24. This FF2
The output of the inverter 28 via the OR gate 32 and the output from the duty ratio selection circuit 30 are input to the reset manual power R of No. 2. Then, the Q output of the FF 22 is input to the gate circuit 16 and superimposed on the audible sound signal, and the amplification circuit 34
The signal is input to a sound generation circuit 38 composed of a speaker 36.

On the other hand, the duty ratio selection circuit 30 for selecting the duty ratio of the high frequency signal is connected to a ROM 40 in which data of the duty ratio to be preset in the up/down counter 20 is stored.
．． and an address counter 42 that reads data from the ROM 40.

Data outputs D1 to D of the ROM 40 are input to preset manual inputs P1 to P5 of the up/down counter 20,
The output of the inverter 28 is input to the chip select input σ which controls whether the ROM 40 is active or inactive. Furthermore, address human power A of ROM40.

The outputs Q1 to Q of the address counter 42 are inputted to . Carry output C of this address counter 42
is input to the OR gate 32 and the audible sound generation circuit 14,
The output of the inverter 28 is input to the reset human power R. Furthermore, the clock manual power φ has ROM40 at regular intervals.
A timing signal generation circuit 44 determines the timing for changing the duty ratio by switching to the duty ratio data output from the frequency divider circuit 4, and this circuit also receives a constant period signal (2048 Hz in this embodiment) from the frequency divider circuit 4. is inputting.

The operation of this circuit will be explained below using the time charts of FIGS. 2 and 3.

The data stored in R, 0M40 is configured to decrease each time the count value supplied to addresses A1 to A increases, as shown in FIG.

In this state, when the set time arrives and the output of the reference circuit 12 changes from rLJ to "H", the up/down counter 20. FF22. Address counter 38 is released from reset and ROM 40 becomes active. The audible sound generating circuit 14 is also inactive and supplies an audible signal to the gate circuit 16 as shown in FIG. At the same time, the up/down counter 20 receives a constant periodic signal (
IMHz) Th starts counting up, and after a certain period of time, a positive single pulse is output from the carry output via the inverter 24. When this single pulse rises, the up/down counter 20 is stored in the ROM 40.
The first data (11111) of FF22 is preset, and as the single pulse falls, the Q output of FF22 becomes "I4".

The output is inverted to rLJ. By inverting this Q output, the up/down counter 20 becomes a down counter and starts a down run.

After a certain period of time has elapsed, the up/down counter 2
The value of 0 becomes 0, and a positive single pulse is output from the carry output via the inverter 24. As a result, the output of FF20 is inverted, and the up/down counter 2
The data output (11111) from R,0M40 is preset to 0, and the up/down counter 20 becomes an up counter. Thereafter, as soon as the constant periodic signal (IMHz) input to the up/down counter 20 falls, a positive single pulse is output from the carry output via the inverter 24. As a result, the amplifier down counter 20 again outputs data from the ROM 40 (111
11) is precented and becomes a down counter. This operation is repeated from now on.

As this operation is repeated, the timing signal generation circuit 4
A positive single pulse is generated from 4, and the address counter 420 increments the count value by one step.

As a result, data is output from R, 0M40 (11110
) is output and preset in the amplifier down counter 20. As a result, the amplifier down counter 20
The up-count period of increases and the down-count period of decreases. Thereafter, each time a timing signal is generated, the value of data preset in the amplifier down counter 20 decreases, and accordingly, the amplifier count period of the up/down counter 20 increases and the down count period decreases. As a result, the Q output signal of FF22 becomes approximately 32K, with the duty ratio decreasing stepwise as shown in Figure 2.
It becomes a Hz signal. The Q output signal of this F F 22 is
As shown in FIG. 3, the signal is superimposed on the audible signal from the audible sound generation circuit 14 by the gate circuit 16 and input to the sound generation circuit 38. As a result, the speaker 36 generates an audible sound whose volume gradually decreases.

Then, when the address counter 42 performs a counting operation and a positive single pulse is generated at the carry output C, the FF
22 is temporarily reset, and the audible sound generation circuit 14 generates the next sound. After this, the duty ratio of the high-frequency signal to be superimposed again is about 9 to the initial magnitude, and gradually decreases as time passes, as before.

In this manner, the volume can be gradually reduced by superimposing a high frequency signal having a higher frequency than the audible frequency and a gradually decreasing duty ratio on the melody to be generated. In this case, external components such as resistors and capacitors are not unnecessary and can be very easily incorporated into the integrated circuit. Furthermore, since it is only necessary to superimpose a signal having a high frequency inaudible to the human ear and having a variable duty ratio on the waveform of the sound to be generated, it can be used with any sound waveform.

In this embodiment, the present invention is applied to a melody sound whose volume gradually decreases over time. However, by replacing the data stored in the ROM 40, the volume can be gradually increased. You can freely increase or decrease the volume.

Furthermore, in this embodiment, the high frequency signal with a variable duty ratio is taken out from the frequency divider circuit 4 of the clock, but it is also possible to provide an independent oscillator, and it is also possible to use it in a sound generation circuit other than a clock. It is.

As described above, according to the present invention, in an audio frequency signal,
A high frequency signal whose frequency is higher than that of an audio frequency signal and whose duty ratio can be varied is fully superimposed, and this duty ratio?
By making it variable, the volume of any sound waveform can be freely varied. Furthermore, this volume variable circuit does not require external components such as resistors and capacitors, and it is also easy to incorporate into an integrated circuit, so it has the advantage of being cheaper than conventional volume variable circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram according to an embodiment of the present invention. FIG. 2 is a time chart in FIG. 1. FIG. 3 is a time chart in FIG. 1. Is Fig. 4 the memory contents of the ROM in Fig. 1? Table showing. 4... Frequency dividing circuit, 14... Audible sound generation circuit, 16... Gate circuit, 18... Duty ratio variable circuit, 30... Duty ratio selection circuit, 44... Timing signal generation circuit. that's all

Claims (1)

[Claims] (1) An audio frequency signal generation circuit that generates all audio frequency signals having arbitrary waveforms, a high frequency signal generation circuit that generates a high frequency signal having a higher frequency than the audio frequency signal, and a high frequency signal generation circuit that generates a high frequency signal having a higher frequency than the audio frequency signal; A variable duty ratio circuit that varies the duty ratio, a duty ratio selection circuit that selects one from a plurality of stored duty ratios and supplies it to the variable duty ratio circuit, and a duty ratio selection circuit that selects one from a plurality of stored duty ratios and supplies it to the variable duty ratio circuit. a timing signal generation circuit that supplies all signals for selecting all duty ratios; gate means for superimposing the high frequency signal on the audible frequency signal; and a sound generation circuit for generating an audible sound by the signal from the gate means;
A volume variable circuit characterized by selectively varying the volume of audible sounds. (2. The volume variable circuit as set forth in claim 1, which is characterized in that the time reference signal of a clock is frequency-divided and extracted as a high-frequency signal. (3) Claim 1 or 3. The volume variable circuit according to item 2, wherein the duty ratio selection circuit is configured to select a duty ratio from a larger duty ratio to a smaller duty ratio sequentially as time passes.