JPH0531588Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a watch with a sleep function that can change the time at which a sleep sound is generated.

(Prior art) For example, as a watch with a sleep function,
The one described in No. 55-106392 is known.

In addition to the alarm function, this type of watch has a sleep function, and when you set it to sleep mode when you go to sleep, a sleep sound will be generated for a certain period of time, and the sleep sound will gradually become softer, allowing you to fall asleep. We make it easy.

In addition, it is equipped with a switch that allows you to change the sleep sound generation time (for example, 4 minutes or 8 minutes).
It is possible to select any one according to the user's preference.

(Problem to be solved by the invention) However, in the above-mentioned conventional watches with a sleep function, the sleep sound generation time changeover switch is changed over and over again, or the changeover switch itself has a chattering operation, so that the desired sleep time can be set. A problem often occurred where the time was set to a different time.

(Means for Solving Problems and Its Effects) The present invention was made to eliminate the above-mentioned drawbacks, and includes a guide switch that turns on at a preset time, and a switch that turns on and off by external operation to instruct sleep operation. a sleep switch, a sound stop switch that is turned on and off by external operation, a gate circuit that passes the on operation signal of the reference switch when the sound stop switch is turned off, and the on signal of the reference switch is output from the gate circuit. an alarm circuit that outputs an alarm signal when the sleep switch is turned on; a sleep circuit that outputs a sleep signal in response to a sound-off operation signal of the sound-stopping switch when the sleep switch is on; A sleep counter that starts counting in response to the stop-off operation signal and outputs a sleep stop signal that causes the sleep circuit to stop outputting the sleep signal after a certain period of time, and generates different notification sounds depending on the sleep signal and alarm signal. a notification circuit to
A timepiece with a sleep function, comprising: a volume control circuit that reduces the volume of a notification sound emitted from the notification circuit every predetermined period of time in accordance with the count value of the sleep counter, A changeover switch that changes the generation time, a frequency divider circuit that divides the frequency of a clock signal with a constant period, a holding circuit that reads and outputs the switching operation signal of the changeover switch, and a signal from the holding circuit that divides the clock signal or the divided clock signal. The device is configured to include a switching gate circuit that selects an output signal of the circuit and outputs it to the sleep counter and outputs it as a read timing signal of the holding circuit.

In the alarm mode, the mute switch is set to the mute off state, and when the indicator switch is turned on, the indicator switch's on signal passes through the gate circuit, and while this on signal is output, the alarm circuit is activated. An alarm signal is output from the alarm circuit to the notification circuit, and an alarm sound is emitted.

In addition, in sleep mode, when the sleep switch is set to the on state, and the alarm is set (reference set) and the mute switch is turned to the mute off state, a sleep signal is output from the sleep circuit, and the sleep signal causes the alarm to go to sleep. The counter starts counting, and based on this count value, the volume control circuit controls the notification sound emitted from the notification circuit to decrease at regular intervals. That is, the sleep sound is emitted such that the generated sound becomes smaller in stages. Then, after a certain period of time has elapsed, a sleep stop signal is output from the sleep counter, and the generation of the sleep sound is thereby stopped.

Further, the switch output of the changeover switch is outputted to the changeover gate circuit through the holding circuit, the changeover gate circuit selects the clock signal or the output frequency-divided by the frequency divider circuit, and the selected output is supplied to the sleep counter. For example, a count of 4 minutes or 8 minutes is performed. In this case, the above holding circuit reads and outputs the switch output of the changeover switch in accordance with the generation timing of the pulse output signal of the changeover gate circuit. No malfunction occurs when setting the sound generation time.

(Example) An example of the present invention will be described below based on the drawings.

FIG. 1 is an electrical circuit diagram of a watch with a sleep function. In the figure, S ₁ is a sleep switch, S ₂ is a reference switch, S ₃ is a sound stop switch, and S ₄ is a sleep sound generation time changeover switch, and each switch S ₁ to _{S 4}
When closed, it is connected to the low side, and when it is opened, it is connected to the high side via a resistor.

The reference switch _S2 is connected to a gate circuit 3 via an inverter 1, and the output B of the gate circuit 3 is input to an alarm circuit 5. The alarm circuit 5 includes an inverter 7, one-shot multivibrator circuits 9 and 11, and a flip-flop 1.
3. It is composed of an inverter 15, and an alarm signal I is output from the inverter 15. The alarm signal I is input to the notification circuit 17 through the resistor R ₀ and also to the OR circuit 19 for melody, and the melody signal M is input from the OR circuit 19 to the notification circuit 17 . A speaker 21 is connected to the output side of the notification circuit 17, and an alarm sound is generated by both signals I and M.

The sound stop switch _S3 is connected to the input side of the gate circuit 3 via an inverter 25, and is also connected to a sleep circuit 27. The sleep circuit 27 includes an inverter 29, one-shot multivibrator circuits 31 and 33, a flip-flop 35, an inverter 37, and a NOR circuit 39.
and 41. The output J of the inverter 37 and the output A of the sleep switch _S1 are input to the NOR circuit 39, and the sleep signal K is output from the NOR circuit 39. This sleep signal K is input to the OR circuit 19, and the melody signal M is output to the notification circuit 17, as well as to the decoder 47 of the volume control circuit 45 and the switching circuit 53, which will be described later.
The signal is input to a NAND circuit 65. Further, the outputs E, D, F, and G of the one-shot multivibrator circuits 9, 11, 31, and 33 are input to the input side of the other NOR circuit 41, and the output signals E,
In response to D, F, and G, a reset signal L is output from the NOR circuit 41 to the sleep counter 49.

The sleep counter 49 uses a 2Hz clock signal.
1 minute or 2 minutes based on CL 4 times
By outputting volume signals Q ₁ to _{Q 3} every minute or every 2 minutes, and counting each signal 4 times, a carry signal (sleep stop signal) is generated after 4 minutes or 8 minutes.
T is output to the flip-flop 35 of the sleep circuit 27, and generation of the sleep signal K is stopped.

The volume control circuit 45 is composed of a decoder 47 and a plurality of resistors R ₁ to R ₄ . In this embodiment, in order to reduce the noise generated during sleep in four levels, the four resistors are connected to R ₁ to _{R 4} . The resistance value is configured to gradually increase.

Further, a frequency dividing circuit 51 and a switching gate circuit 53 are provided on the input side of the sleep counter 49, and a holding circuit 55 is provided between the switching gate circuit 53 and the switching switch _S4 when sleep sound is generated. ing.

The frequency divider circuit 51 generates a 2 Hz clock signal CL
is divided in half to output a 1 Hz pulse signal R to the switching gate circuit 53.

The switching gate circuit 53 is composed of four NAND circuits 59, 61, 63 and a gate circuit 65, and the NAND circuit 59 has a clock signal.
CL and the output Q of the gate circuit 65 are inputted, and the output R of the frequency dividing circuit 51 and the above output Q are inputted to the other NAND circuit 61, and both NAND circuits 59, 6
The output of 1 is input to the NAND circuit 63, and the output S from the NAND circuit 63 is input to the sleep counter 49. Further, the output P of the holding circuit 55 is inputted to the gate circuit 65 that outputs the output Q, the changeover switch _S4 is connected to the input terminal D of the holding circuit 55, and the clock terminal φ is connected to the NAND circuit 55. 63 is inputted via an inverter 67. Then, by operating the changeover switch _S4 , the sleep sound generation time is selected to be 4 minutes or 8 minutes. In this embodiment, 8 minutes is selected by opening, and 4 minutes is selected by closing.

Next, the operation of such a watch with a sleep function will be explained based on the time chart shown in FIG. Note that the description of the alarm mode will be omitted.

First, set the sleep mode, that is, the sleep switch _S1 to the on (closed) state, the reference switch _S2 to the set (open) state, and the sleep sound generation time selector switch _S4 to the 8 minute side (open). Then, at time _t1 , when the sound stop switch _S3 is turned to the sound stop off (closed) state, the output C of the inverter 25 becomes high due to the operation of the sound stop switch _S3 . On the other hand, the output of the inverter 29 becomes low, and the pulse output F only from the one shot multi-vibrator circuit 31 rises to a high state. and,
In the flip-flop 35, the output G is in the low state and only the output F is in the high state, so in response to this rise, the output J of the inverter 37 falls to the low state, and the sleep signal K is output from the NOR circuit 39. .

This sleep signal K is the OR circuit 1 for melody.
9 and also to the reset terminal of the decoder 47 of the volume control circuit 45. At the same time, the output F of the one-shot multivibrator circuit 31 is input to the NOR circuit 41, and the reset signal L is input from the NOR circuit 41 to the reset terminal of the sleep counter 49. Then, at the same time as the melody signal M is output from the OR circuit 19 to the notification circuit 17 based on the sleep signal K,
Counting is started in the sleep counter 49 by the reset signal L, and 2-minute signals Q ₁ to _{Q 3} are sequentially output to the decoder 47 every 2 minutes.
In the decoder 47, based on the bipartite signals _Q1 to _Q3 , the resistors _R2 to _R4 having gradually larger resistance values are
A signal is output to the notification circuit 17 by switching every minute,
During the sleep sound generation time of 8 minutes, the sleep melody sound is generated from the speaker 21 so that the tone becomes gradually softer in four stages. After eight minutes, a carry signal T is sent from the sleep counter 49 to the flip-flop 35, and the sending of the sleep signal K is stopped, and the generation of the sleep melody sound is stopped.

In this case, the sleep counter 49 counts the number of pulses of the pulse signal S input to the input terminal φ. That is, in the case of 8-minute counting, it is based on the output R in FIG. 2, and on the other hand, in the case of 4-minute counting, it is based on the clock signal CL, and these outputs R
To switch between the clock signal CL and the clock signal CL, use the changeover switch.
This is done by the output Q of the gate circuit 65 which operates in conjunction with the operation of _S4 . In other words, when the sleep sound generation time is 8 minutes, the switch and the output O are in the high state, so the output Q of the gate circuit 65 is in the low state, and the NAND circuit 61 of the switching gate circuit 53 is selected and 1/2 The frequency-divided pulse signal R of 1 Hz is inputted as an output S to the sleep counter 49. On the other hand, when the sleep sound generation time is 4 minutes, the switch output O is in the low state, so the output Q of the gate circuit 65 is in the high state, and the other NAND circuit 59 is selected. The signal CL is output to the sleep counter 49 as the output S.
Each clock is counted by counting the number of pulses of the input signal.

In addition, in the holding circuit 55 provided between the changeover switch _S4 and the changeover gate circuit 53, the switch output O input to the input terminal D is read as the output P every time the pulse signal of the output S falls. Output. Therefore, in the conventional case without the holding circuit 55, the changeover switch _S4 was switched continuously in a short period of time, and the chattering operation of the changeover switch _S4 itself affected the gate output Q. In this embodiment, the output O of the changeover switch _S4 is
is checked every time the clock signal S input to the sleep counter 49 falls _.
The 8-minute signal or the 4-minute signal is output in a stable state without fluctuation even when the switching operation is performed continuously, and the sleep sound generation time can be set reliably.

(Effects of the Invention) As explained above, according to the present invention, the output signal of the sleep sound generation time changeover switch is checked in the holding circuit every time the clock signal rises, so that the changeover switch chattering, Even if the changeover switch is operated continuously, it is now possible to avoid errors in setting the sleep sound generation time.

[Brief explanation of the drawing]

1 and 2 relate to an embodiment of the present invention, in which FIG. 1 is a circuit diagram showing an outline of the electrical system of the watch, and FIG. 2 is a time chart of signals of various parts. 3...pass gate circuit, 5...alarm circuit,
17...Notification circuit, 27...Sleep circuit, 45
... Volume control circuit, 49 ... Sleep counter,
51... Frequency dividing circuit, 53... Switching gate circuit, 5
5...Holding circuit, _S2 ...Standard switch, _S3 ...Sound stop switch, _S4 ...Selector switch, I...Alarm signal, K...Sleep signal.

Claims (1)

[Scope of claim for utility model registration] A guide switch that turns on at a preset time, a sleep switch that turns on and off by external operation to instruct sleep operation, a stop switch that turns on and off by external operation, and a stop switch that turns on and off by external operation. a gate circuit that passes an on operation signal of the reference switch when the switch is turned off, an alarm circuit that outputs an alarm signal when the on signal of the reference switch is output from the gate circuit, and the sleep switch is turned on. a sleep circuit that outputs a sleep signal in response to a sound-off operation signal of the sound-stopping switch; a sleep counter that outputs a sleep stop signal that stops outputting the sleep signal from the circuit; a notification circuit that generates different notification sounds depending on the sleep signal and the alarm signal; A volume control circuit that reduces the volume of a notification sound emitted from the circuit every fixed period of time; A clock with a sleep function that is equipped with a changeover switch that changes the generation time of the sleep sound by external operation; A frequency dividing circuit that divides the frequency; a holding circuit that reads and outputs the switching operation signal of the changeover switch; and a signal from the holding circuit that selects the clock signal or the output signal of the frequency dividing circuit and outputs it to the sleep counter. and a switching gate circuit that outputs a read timing signal for the holding circuit.