JPH0446236Y2 - - Google Patents

Description

[Detailed description of the invention] [Field of industrial application] The present invention relates to an electronic watch with an alarm function, which can store the alarm time used on a daily basis and set a different alarm only once when necessary. The present invention relates to an alarm clock that performs an alarm operation at a certain time, and is reset to a daily alarm time after the alarm operation.

[Prior Art] Today, electronic clocks with a built-in crystal oscillator are extremely widely used because they are highly accurate, easy to downsize, and can easily be provided with additional functions such as an alarm function.

Electronic watches with this alarm function usually
It is possible to set a single alarm time, and if the alarm set switch is turned on, the alarm notification sound can be sounded at the same time every day.

Note that some electronic watches can store multiple alarm times.

[Problems that the invention aims to solve] Once an alarm clock is set, it is possible to make the alarm sound sound at the same time every day, but it is possible to make the alarm sound sound at the same time every day, such as on Sundays. When changing the alarm time, users sometimes forget to change the alarm time back to their usual wake-up time, which can be inconvenient. Furthermore, even in an alarm watch that can store a plurality of alarm times, the user must select a set alarm time and perform a switching operation, and the user may forget to perform the switching operation.

[Means for solving the problem] In an alarm clock having a reference signal generation circuit, a time counter, an alarm memory, a time adjustment circuit, a coincidence detection circuit, a sound generation circuit, etc., it is possible to preset load the stored value of the alarm memory. a second memory circuit; an alarm time correction circuit for changing the value stored in the second memory circuit; and a second coincidence detection circuit for detecting a match between the value stored in the second memory circuit and the count value of the time counter. , a load signal generation circuit is provided that outputs a load signal to the second memory circuit based on a coincidence signal output later among the coincidence signal from the second coincidence detection circuit and the coincidence signal from the coincidence detection circuit. , the sound generation circuit generates an alarm notification sound in response to the coincidence signal from the second coincidence detection circuit.

[Function] Since the present invention is provided with a second memory circuit in addition to the conventional alarm memory, a specific alarm time is stored in the second memory circuit. The alarm notification sound can be emitted from the sound generation circuit at the alarm time, and
When the stored value in the second memory circuit matches the count value in the time counter, a coincidence signal outputted from the second coincidence detection circuit is inputted to the load signal generation circuit, and the alarm memory When the stored value matches the count value in the time counter, a match signal is output from the match detection circuit, and this match signal is also input to the load signal generation circuit. The load signal generation circuit outputs a load signal, and the load signal allows the second memory circuit to be preset loaded with the stored value of the alarm memory.

Therefore, the second memory circuit stores the second memory value based on the stored value.
Once a match signal is output from the match detection circuit,
The memory value of the alarm memory is read by the load signal, and the specific alarm time stored in the second memory circuit is erased only once, and after the second coincidence detection circuit outputs the coincidence signal, the alarm memory is The alarm time will be returned to the normal alarm time stored in the memory.

[Embodiment] The embodiment of the present invention uses a reference signal generation circuit, a time counter, and a time counter provided in a conventional alarm watch.
Alarm memory, time adjustment circuit and sound generation circuit,
A second memory circuit, a second coincidence detection circuit, a load signal generation circuit, and an alarm time adjustment circuit are provided, and an on/off control circuit is also provided to prevent an increase in the number of operation switches.

As a circuit example of this embodiment, as shown in FIG. 1, a reference signal generation circuit 10 is composed of an oscillation circuit 12 such as a crystal oscillator and a frequency divider 14, and outputs a plurality of reference signals having different frequencies. It also has a second counter 18, a minute counter 20, and an hour counter 22.
a time counter 16 which outputs a time signal based on the reference signal from the reference signal generation circuit 10, and an alarm memory 32 which stores an alarm time and is comprised of a minute memory 34 and an hour memory 36.
and a coincidence detection circuit 38 that detects coincidence between the stored value of the alarm memory 32 and the counter value of the time counter 16, and the time counter 16 based on the operation of the minute correction switch 24, hour correction switch 26, and changeover switch 28. A time correction circuit 3 capable of correcting the count value of and storing the alarm time in the alarm memory 32.
Having 0 is similar to a conventional alarm watch.

The counter value outputs of the minute counter 20 and hour counter 22 in the time counter 16 are sent to the coincidence detection circuit 38 and the display switching circuit 1
Time display circuit 14 having a display element via 28
6, a newly installed second coincidence detection circuit 46
shall also be sent to

Further, a newly provided second memory circuit 40 includes a second minute memory 42 that can preset load the stored value of the minute memory 34 in the alarm memory 32.
and a second hour memory 4 into which the stored value of the hour memory 36 in the alarm memory 32 can be preset loaded.
4, and an up-count-down count control terminal of the second minute memory 42 and a second hour memory 44.
The up count down count control terminal is connected to the alarm time adjustment circuit 70 described later, the φ input terminal of the second minute memory 42 is also connected to the alarm time adjustment circuit 70, and the carry signal output terminal of the second minute memory 42 is connected to the alarm time adjustment circuit 70, which will be described later. A preset load control input terminal of the second minute memory 42 and a preset load control input terminal of the second time memory 44 are connected to a load signal generation circuit 48, which will be described later. The stored outputs of the second minute memory 42 and the second hour memory 44 are sent to the second coincidence detection circuit 46 and sent to the time display circuit 148 via the display switching circuit 128.

Further, the coincidence signal output terminal of the coincidence detection circuit 38 is connected to a load signal generation circuit 48, and the coincidence signal output terminal of the second coincidence detection circuit 46 is connected to the load signal generation circuit 48 and a snooze circuit 106, which will be described later.

This load signal generation circuit 48 is composed of two flip-flops, four AND circuits, and two OR circuits, and connects the output terminal of the coincidence detection circuit 38 to the set input terminal of the first flip-flop 50 and the second AND circuit. The input terminal of the circuit 56 and the negative input terminal of the third AND circuit 58 are connected, and the output terminal of the second coincidence detection circuit 46 is connected to the second flip-flop 52.
set input terminal, the first AND circuit 54 and the second
The Q output terminal of the first flip-flop 50 is connected to the input terminal of the first AND circuit 54 and the input terminal of the third AND circuit 58, and the Q output terminal of the second flip-flop 52 is connected to each input terminal of the AND circuit 56. Connect the terminal to the input terminal of the third AND circuit 58,
The output terminals of the first AND circuit 54, the second AND circuit 56, and the third AND circuit 58 are connected to the first OR circuit 6.
0 to the input terminal of the second OR circuit 64. Further, a fourth AND circuit 6 has one input terminal connected to the changeover switch 28 and another input terminal connected to the frequency divider 14 in the reference signal generation circuit 10.
The output terminal of the second OR circuit 64 is connected to the reset input terminal of the first flip-flop 50 and the second flip-flop 52.
It is connected to the preset load control input terminal of the second minute memory 42 and the preset load control input terminal of the second hour memory 44 in the memory circuit 40.

In this embodiment of the alarm watch according to the present invention, the changeover switch 28 is turned on, and the minute adjustment switch 24 and the hour adjustment switch 26 are operated in the same manner as in the conventional alarm watch to change the alarm memory 32.
When storing the alarm time, as shown in FIG. 2, when the changeover switch 28 is turned on and the A signal becomes H level, the fourth AND circuit 62 opens.
The φ ₀ reference signal passed through the fourth AND circuit 62 is
This φ ₀ reference signal passes through the second OR circuit 64 and is output as the D signal as a load signal. 42 and the second hour memory 44 are always loaded with the stored values of the minute memory 34 and the hour memory 36 in the alarm memory 32.

Therefore, when the alarm time is stored in the alarm memory 32 by the minute adjustment switch 24 and the hour adjustment switch 26, this alarm time is immediately stored in the second alarm time.
It will be preset in the memory circuit 40,
The value stored in the second memory circuit 40 is displayed on the time display circuit 146 via the display switching circuit 128, so by looking at the time display circuit 146, you can operate the minute correction switch 24 and the hour correction switch 26 to set the alarm. You can set the time.

When the alarm time stored in the second memory circuit 40 and the count value of the time counter 16 match, a match signal is output from the second match detection circuit 46, and this match signal activates the snooze circuit 106, causing the sound generation circuit 120 to It is possible to generate an alarm notification sound.

When the stored value of the alarm memory 32 and the stored value of the second memory circuit 40 match in this way, the load signal generation circuit 48 outputs a match signal from the match detection circuit 38 as shown in FIG. The first flip-flop 50 is set to the set state by the H level signal output as the B signal, and the second flip-flop 50 is set to the set state.
The second flip-flop 52 is set to a set state by the H level signal output as the C signal as a coincidence signal from the coincidence detection circuit 46, and the P1 signal which is the Q output of the first flip-flop 50 and the Q output of the second flip-flop 52 are output. The P2 signal becomes H level, and the output of the first AND circuit 54 is P3.
The P5 signal, which is the output of the signal and the second AND circuit 56, also goes to H level, and this H level signal passes through the first OR circuit 60 and the second OR circuit 64 to the first flip-flop 50 and the second flip-flop 52.
Since the P1 signal returns to the reset state,
A short H pulse signal appears in the P2 signal, P3 signal, and P5 signal, and this H pulse signal is outputted from the second OR circuit 64 as a load signal to the D signal.

This load signal is sent to the second minute memory 42 and the second hour memory 44 in the second memory circuit 40, causing the second minute memory 42 to load the stored value of the minute memory 34 in the alarm memory 32, and causing the second minute memory 42 to load the stored value of the minute memory 34 in the alarm memory 32. Although the stored value of the hour memory 36 in the alarm memory 32 is loaded into the alarm memory 32, the stored value of the minute memory 34 and the second minute memory 42 are loaded from the beginning.
Since the stored values of the hour memory 36 and the second hour memory 44 are the same,
The alarm time in the second memory circuit 40 is not changed, and the alarm notification sound can be generated from the sound generation circuit 120 at the same time every day.

When a specific alarm time different from the usual alarm time is stored in the second memory circuit 40, the stored value is corrected using a correction direction determination signal and a clock signal from the alarm time correction circuit 70, which will be described later. , the correction direction determination signal is input to the up-count-down count control terminal of the second minute memory 42 and the up-count-down count control terminal of the second hour memory 44, and for example, when the E signal, which is the correction direction determination signal, is at L level. In this case, the second minute memory 42 and the second hour memory 44
is in an up-count state, and the second minute memory 42
Up-counting is performed based on the pulse of the clock signal input to the φ input terminal of the clock, and when the E signal is at the H level, the second minute memory 42 and the second hour memory 44 are put into a down-counting state and the Since down counting is performed based on the pulse of the clock signal input to the φ input terminal of the second memory circuit 42, the stored value of the second memory circuit 40 can be corrected.

In this way, for example, if the second memory circuit 40 stores an alarm time that is later than the normal alarm time, when the normal alarm time comes, the count value of the time counter 16 and the value stored in the alarm memory 32 match, 2, as shown in FIG.
is set to the first flip-flop 5.
The P1 signal, which is a Q output of 0, is set to H level. Thereafter, at a specific alarm time stored in the second memory circuit 40, an H level coincidence signal is output to the C signal output from the second coincidence detection circuit 46.
This coincidence signal passes through the first AND circuit 54, which is open because the P1 signal is at the H level, and further passes through the first OR circuit 60 and second OR circuit 64 to the first flip-flop 50 and second flip-flop 5.
2 is set to the reset state. Therefore, the coincidence signal from the second coincidence detection circuit 46 becomes a short H pulse-like signal, and this H pulse signal is the second one in the D signal.
This is used as a preset load signal to the memory circuit 40, and causes the second memory circuit 40 to load the stored value of the alarm memory 32.

Therefore, when a coincidence signal is output from the second coincidence detection circuit 46, the second memory circuit 40 corrects its stored value to the value stored in the alarm memory 32, and performs the second coincidence detection at a specific alarm time. Once the coincidence signal is output from the circuit 46, it is automatically corrected to the daily alarm time stored in the alarm memory 32.

The coincidence signal from the second coincidence detection circuit 46 is also sent to the snooze circuit 106, and the snooze circuit 106 is activated using this coincidence signal as a trigger.A notification signal is output from the snooze circuit 106 and an alarm is output from the sound generation circuit 120. A notification sound will be emitted.

Further, when a specific alarm time earlier than the usual alarm time is stored in the second memory circuit 40, when the stored value of the second memory circuit 40 and the count value of the time counter 16 match, a second coincidence detection is performed. An H-level coincidence signal is outputted as a C signal from the circuit 46, and this coincidence signal activates the snooze circuit 106, allowing the sound generation circuit 120 to generate an alarm notification sound, and as shown in FIG. , is the Q output of the second flip-flop 52.
When the P2 signal becomes H level and after the required time, the match detection circuit 38 outputs an H level match signal to the B signal, the P1 signal, which is the Q output of the first flip-flop 50, also becomes H level, and the time counter 16 starts counting. When the value progresses and the match signal from the match detection circuit 38 is no longer output, and the B signal returns to L level, the third AND circuit 58 sets its output P4 signal to H level, and this H level signal becomes the first Since the first flip-flop 50 and the second flip-flop 52 are reset via the OR circuit 60 and the second OR circuit 64, a short H pulse signal is output as the output signal of the third AND circuit 58. Since the H pulse output from the third AND circuit 58 is used as a load signal to the second memory circuit 40 by the D signal via the first OR circuit 60 and the second OR circuit 64, this load signal 2 memory circuit 40 will preset load the stored value of alarm memory 32.

Therefore, a specific alarm time can be set as a second alarm time rather than the normal alarm time stored in the alarm memory 32.
When stored in the memory circuit 40, the snooze circuit 106 is activated by the coincidence signal from the second coincidence detection circuit 46 at a specific alarm time, thereby making it possible to generate the alarm notification sound from the sound generation circuit 120. , a coincidence signal is output from the coincidence detection circuit 38 at the normal alarm time, and when the count value of the time counter 16 exceeds the alarm time and the output of the coincidence signal from the coincidence detection circuit 38 is stopped, the load signal generation circuit 48 The stored value of the second memory circuit 40 is automatically returned to the stored value of the alarm memory 32 by the load signal from the alarm memory 32 . That is, the snooze circuit 1 is activated at a specific alarm time.
06 is activated only once, and then the value stored in the second memory circuit 40 is corrected to the value stored in the alarm memory 32.

The alarm time correction circuit 70 for correcting the stored value of the second memory circuit 40 includes a first correction switch 6 whose one end is connected to the H level power supply.
The other end of the second correction switch 68 is connected to each input terminal of the fifth AND circuit 72, the seventh AND circuit 84, and the third OR circuit 80, and the other end of the second correction switch 68, one end of which is connected to the H level power supply, is connected to the sixth The output terminal of the fifth AND circuit 72 is connected to the input terminals of the AND circuit 74, the seventh AND circuit 84, and the third OR circuit 80, and the output terminal of the fifth AND circuit 72 is connected to the third AND circuit.
A second input terminal is connected to the set input terminal of flip-flop 76.
The Q output terminal of the flip-flop 76 is connected to the negative input terminal of the sixth AND circuit 74.
The output terminal of the flip-flop 78 is connected to the set input terminal of the fourth flip-flop 78, and the Q output terminal of the second flip-flop 78 is connected to the negative input terminal of the fifth AND circuit 72. The Q output terminal is connected to each up-count/down-count control terminal of the second minute memory 42 and second hour memory 44 in the second memory circuit 40 to serve as a decision signal,
The output terminal of the third OR circuit 80 is connected to each reset input terminal of the third flip-flop 76 and the fourth flip-flop 78 via an inverter 82, and is also connected to an on/off control circuit 90, which will be described later.
The output terminal of the seventh AND circuit 84 is connected to the input terminal of the ninth AND circuit 88, as well as to an on/off control circuit 90 and a snooze circuit 106, which will be described later.
The _φ1 reference signal from the reference signal generation circuit 10 is inputted via the AND circuit 86, and the eighth AND circuit 86
One input terminal is connected to the on/off control circuit 90 as a negative input type, and the output terminal of the ninth AND circuit 88 is connected to the second division memory 42 in the second memory circuit 40.
It is connected to the φ input terminal of.

The on/off control circuit 90 connects each input terminal of the tenth AND circuit 92 and the twelfth AND circuit 100 and the negative input terminal of the fourth OR circuit 98 to the output terminal of the third OR circuit 80 in the alarm time adjustment circuit 70. The input terminals of the 11th AND circuit 96 and the 13th AND circuit 102 are connected to the output terminal of the 7th AND circuit 84 in the alarm time adjustment circuit 70, and the output terminal of the 10th AND circuit 92 is connected to the first pulse The output terminal of the eleventh AND circuit 96 is connected to the input terminal of the fourth OR circuit 98, and the output terminal of the fourth OR circuit 98 is connected to the reset input terminal of the first pulse counter 94. In addition, the carry signal output terminal of the first pulse counter 94 is connected to the negative input terminal of the eighth AND circuit 86 in the alarm time adjustment circuit 70, and the on/off control circuit 90 is connected to the snooze circuit 106, which will be described later. Each negative input terminal of the 10th AND circuit 92, the 11th AND circuit 96, and the 12th AND circuit 100 and the 13th AND circuit 1
02 and is also connected to a snooze circuit 106, which will be described later. Further, both output terminals of the 12th AND circuit 100 and the 13th AND circuit 102 are connected to a display switching circuit 128, which will be described later, via a fifth OR circuit 104. It is assumed that the tenth AND circuit 92 is of a three-input type, and the _φ3 reference signal is input to the remaining one input terminal.

Therefore, in the alarm time correction circuit 70, when the first correction switch 66 is turned on and the R1 signal is set to the H level, thereby setting the third flip-flop 76 to the set state, the sixth AND circuit 74 is closed.
This will keep the R4 signal at L level,
Even if the second correction switch 68 is turned on and off, the reset state of the fourth flip-flop 78 can be maintained, and as shown in FIG. 40
a second minute memory 42 and a second hour memory 44 in
can be fixed in the up count state. After turning on the first correction switch 66 in this way, when the second correction switch 68 is turned on and the R2 signal is set to H level, the output of the seventh AND circuit 84 is
The signal becomes H level, opens the ninth AND circuit 88, sends the _φ1 reference signal as a clock signal to the F signal, and thereby changes the values stored in the second minute memory 42 and second hour memory 44 in the second memory circuit 40. can be increased.

Then, in the on/off control circuit 90, the G signal becomes H.
level, the 10th AND circuit 92 is opened.
Although the pulse of the φ ⁴ reference signal is output to the S1 signal and the first pulse counter 94 starts counting the pulse, the first pulse counter 94 does not start counting within the time until the carry signal is output from the first pulse counter 94. When the 2 correction switch 68 is also turned on, the S2 signal, which is the output of the 11th AND circuit 96, becomes H level, and this S2 signal passes through the 4th OR circuit 98 to the M
Since the signal is set to H level and the first pulse counter 94 is reset, the second correction switch 6
8 and the carry signal is not output from the first pulse counter 94 during a certain period of time, the eighth AND circuit 86 in the alarm time adjustment circuit 70 is kept open, and the second adjustment switch 6
It is possible to sustain the output of the clock signal from the ninth AND circuit 88 when the ninth AND circuit 88 is in the on state. If the intermittent operation of the second correction switch 68 is not performed for a certain period of time or more, the first pulse counter 94 outputs a carry signal and sets the K signal to H level.
The tenth AND circuit 92, the eleventh AND circuit 96, and the twelfth AND circuit 100 in the on/off control circuit 90 are closed, and the alarm time adjustment circuit 7 is closed.
Even if the eighth AND circuit 86 at 0 is closed and the second correction switch 68 is turned on and off, the alarm time correction circuit 70 is prevented from outputting a clock signal.

Note that when the carry signal is not output from the first pulse counter 94, the first correction switch 66
is turned on, and when the G signal becomes H level, the first
The S3 signal, which is the output of the 2-AND circuit 100, becomes H level, and the J signal, which is the output of the fifth OR circuit 104, becomes H level.
When the signal becomes H level, the second memory circuit 40 is displayed in the time display circuit 146 via the display switching circuit 128.
The memorized time will be displayed.

The above operation example is a case where the first correction switch 66 is first turned on and the second correction switch 68 is turned on and off, and when the first correction switch 66 is turned on and off after the second correction switch 68 is turned on,
Since the R2 signal becomes H level first and the R4 signal becomes H level, the fourth flip-flop 78 is set, and the E signal, which is the Q output of the fourth flip-flop 78, becomes H level and the fifth AND circuit 72 is closed, and the H level of the E signal, which is the correction direction determining signal, is not changed by turning on and off the first correction switch 66. Therefore, the down-counting state of the second memory circuit 40 is maintained, and the first correction switch 66 is closed. By causing the F signal to output a clock signal through the intermittent operation, the stored value of the second memory circuit 40 can be decreased.

Furthermore, the snooze circuit 106 connects the set input terminal of the fifth flip-flop 108 and the set input terminal of the second pulse counter 114 to the output terminal of the second coincidence detection circuit 46, and connects the reset input terminal of the fifth flip-flop 108 to the output terminal of the second coincidence detection circuit 46. and the input terminal of the seventh OR circuit 118 are connected to the output terminal of the fourth OR circuit 98 in the on/off control circuit 90, and the input terminal of the fifteenth AND circuit 116 is connected to the seventh AND terminal in the alarm time adjustment circuit 70. It is connected to the circuit 84 and the carry signal output terminal of the first pulse counter 94 in the on/off control circuit 90, and further connected to the fifth flip-flop 10.
The Q output terminal of No. 8 is connected to the input terminal of the sixteenth AND circuit 110 and a display switching circuit 128, which will be described later.
The _φ4 reference signal is input to the other input terminal of the AND circuit 110, and the output terminal of the 16th AND circuit 110 is connected to the φ input terminal of the second pulse counter 114 via the 17th AND circuit 112. The carry signal output terminal of the pulse counter 114 is connected to the negative input terminal of the seventeenth AND circuit 112 and also to the sound generation circuit 120, which will be described later.
The output terminal of the AND circuit 116 is connected to the reset input terminal of the second pulse counter 114 via the seventh OR circuit 118.

Therefore, in this snooze circuit 106,
As shown in the time chart of FIG. 3, both the first correction switch 66 and the second correction switch 68 are turned off, the G signal is at the L level, and therefore the M signal, which is the output of the fourth OR circuit 98, is at the H level. In the case of the level, the reset state of the fifth flip-flop 108 and the second pulse counter 114 is maintained, and the fourth
As shown in the figure, the O signal, which is the output of the second pulse counter 114, is set to the L level, and the sound generation circuit 120 does not generate sound.

Further, when either the first correction switch 68 or the second correction switch 68 is turned on and the M signal is at the L level, the C signal, which is the output signal of the second coincidence detection circuit 46, receives an H level coincidence signal. When output, the fifth flip-flop 108 and the second pulse counter 114 are set, and the N signal becomes H.
At the same time, the O signal from the carry signal output terminal of the second pulse counter 114 also becomes H level, a notification signal is output, and the sound generation circuit 120 generates an alarm notification sound. Then, when the first correction switch 66 or the second correction switch 68 which is in the off state is turned on while the alarm notification sound is being generated, the I signal from the alarm time correction circuit 70 becomes H level and the 15th AND circuit 116 The T1 signal, which is the output signal of
Reset the pulse counter 114 and set the O signal to L.
level and stop the output of the notification signal.

However, since the N signal, which is the Q output of the fifth flip-flop 108, is maintained at the H level, the
Since the φ ₄ reference signal is output to the T2 signal which is the output signal of the 16 AND circuit 110, and the O signal has become L level, the φ ₄ reference signal is output to the 17th AND circuit 1.
The second pulse counter 114 counts this pulse, returns the O signal to the H level again after a certain period of time, and outputs a notification signal.

Then, if both the first correction switch 66 and the second correction switch 68 are turned off, and the G signal is set to L level, the M signal, which is the output of the fourth OR circuit 98 in the on/off control circuit 90, is set to H level. The fifth flip-flop 108 and the second
The pulse counter 114 can be returned to the reset state and the snooze operation can be stopped.

Note that the sound generation circuit 120 is a three-input type 18th
The notification signal from the snooze circuit 106 is input to the AND circuit 122, and the 18th AND circuit 12
Input the audio frequency _φ6 reference signal into 2, and
Similar to the conventional sound generation circuit 120, the _φ5 reference signal for making the alarm notification sound an intermittent sound is input, and the output terminal of the 18th AND circuit 122 is connected to the speaker 126 via the driver 124. Further, the display switching circuit 128 has a negative input terminal connected to the Q output terminal of the fifth flip-flop 108 in the snooze circuit 106, and a normal input terminal connected to the fifth OR circuit 10 in the on/off control circuit 90.
14th AND circuit 130 connected to the output terminal of 4
via the sixth OR circuit 132 to each negative input terminal of the first AND circuit group 134 and each negative input terminal of the third AND circuit group 140, and further to each normal input terminal of the second AND circuit group 136. and each normal input terminal of the fourth AND circuit group 142, and the first
Each output terminal of the AND circuit group 134 and each output terminal of the second AND circuit group 136 are connected to the first OR circuit 138.
to the time display circuit 146 via the output terminals of the third AND circuit group 140 and the fourth AND circuit group 1.
42 output terminals are connected to the time display circuit 146 via the second OR circuit group 144,
The other input terminals of the sixth OR circuit 132 are connected to the changeover switch 28, the input terminals of the first AND circuit group 134 are connected to the time counter 22, and the input terminals of the second AND circuit group 136 are connected to the time counter 22. Second time memory 44 in second memory circuit 40
Each input terminal of the third AND circuit group 140 is connected to the minute counter 20 in the time counter 16, and each input terminal of the fourth AND circuit group 142 is connected to the second minute memory 42 in the second memory circuit 40.

Therefore, when the display changeover circuit 128 turns on the changeover switch 28 and corrects the stored value of the alarm memory 32 by the minute correction switch 24 and the hour correction switch 26, since the A signal is at H level, the sixth OR circuit 132 is set to H level, and the stored value of the second memory circuit 40, into which the stored value of the alarm memory 32 is preset loaded via the second AND circuit group 136 and the fourth AND circuit group 142, is set to the H level. output to the display circuit 146, and the first
When operating the correction switch 60 and the second correction switch 68 to increase or decrease the stored value of the second memory circuit 40, as shown in FIG. 4, since the J signal from the on/off control circuit 90 is at H level, U via the 14th AND circuit 130 and the 6th OR circuit 132
The signal is set to H level and the stored value of the second memory circuit 40 is output to the time display circuit 146. In normal cases, the U signal and L level are output to the first AND circuit group 134 and the third AND circuit group. 140 is opened, and a time signal, which is the count value of the minute counter 20 and hour counter 22 in the time counter 16, is outputted to the time display circuit 146.

As mentioned above, the alarm watch of this embodiment has the second memory circuit 40 in addition to the alarm memory 32, and also has the load signal generation circuit 48. If the alarm time is stored in the second memory circuit 40, an alarm notification sound is generated at the specific alarm time, and then the second memory circuit 4
The memory value of the alarm memory 32 is preset loaded as the memory value of 0 to automatically return to the daily alarm time, and the first correction switch 66 and the second
Since the correction switch 68 doubles as a timer reset switch and a snooze switch by the on/off control circuit 90 and the snooze circuit 106, the number of operation switches can be relatively reduced.

[Effects of the invention] The present invention adds a second memory circuit, a second coincidence detection circuit, and a load signal generation circuit, so that a specific alarm time different from the normal alarm time stored in the alarm memory can be stored in the second memory circuit. The specific alarm time stored in the second memory circuit can be stored in the second memory circuit to generate an alarm notification sound at a specific alarm time.
When a coincidence signal is output from the coincidence detection circuit, the load signal from the load signal generation circuit returns to the daily alarm time stored in the alarm memory.

Therefore, if a specific alarm time different from the usual wake-up time is stored in the second memory circuit, the alarm sound will be emitted only once at the specific alarm time, and the alarm time from the next day onwards will be the same as the usual wake-up time. Since the alarm time is automatically reset to the alarm time, there is no chance of forgetting to reset the alarm time even if you set an alarm time that is different from the normal alarm time just once.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the alarm clock according to the present invention, Fig. 2 is a time chart showing the operation of the load signal generation circuit, and Fig. 3 is a circuit diagram showing the operation of the alarm time adjustment circuit and the on/off control circuit. FIG. 4 is a time chart showing the operation of the snooze circuit 106 and the display switching circuit. 10... Reference signal generation circuit, 16... Time counter, 30... Time correction circuit, 32... Alarm memory, 38... Coincidence detection circuit, 40... Second memory circuit, 46... Second coincidence detection circuit , 48...
Load signal generation circuit, 66...First correction switch, 68...Second correction switch, 70...Alarm time correction circuit, 90...On/off control circuit, 1
06... Snooze circuit, 120... Sound generation circuit, 1
28...Display switching circuit, 146...Time display circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A reference signal generation circuit, a time counter that counts time using a reference signal from the reference signal generation circuit, an alarm memory that stores an alarm time, and an alarm memory that stores the alarm time and the displayed current time. A time adjustment circuit that corrects the time; a coincidence detection circuit that outputs a coincidence signal when the current time counted by the time counter matches the alarm time stored in the alarm memory; and a coincidence detection circuit that outputs an alarm sound in response to the coincidence signal. An alarm clock comprising: a sound generation circuit that can generate a sound; a second memory circuit that can preset load the alarm time stored in the alarm memory; and an alarm time correction circuit that changes the value stored in the second memory circuit. a second coincidence detection circuit capable of outputting a coincidence signal to operate the sound generation circuit when the stored value of the second memory circuit and the count value of the time counter match; and a coincidence signal from the coincidence detection circuit. and a load signal generation circuit to which the coincidence signal from the second coincidence detection circuit is input, and which outputs a load signal to the second memory circuit based on the coincidence signal that is input later among both coincidence signals. A clock with an alarm.