JPH0518719Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Field of Application) The present invention relates to a voice recognition clock that controls clock functions by voice.

(Prior Art) So-called voice recognition clocks have been proposed in which clock functions such as display switching and correction are performed using voice. (Japanese Patent Application Laid-Open No. 58-30695) The feature of these voice recognition clocks is that a predetermined voice is registered, and the clock function is controlled when the voice input after that matches the registered voice. be. (For example, if you register as "Nanji",
If you then input "nanji" by voice, the time will be displayed, etc.) (Problem that the invention aims to solve) However, the previously registered voice is generated in the same way again to control the clock function. This may seem simple, but it is difficult. For example, if you have a cold and your voice has changed, your mental state at that time, or even external conditions such as noise have changed from when you registered, you will not be able to input the same voice as the one you registered. .

For this reason, current voice recognition clocks do not have very high recognition rates, may require repeating the voice many times to control the clock functions, and are often found to be more difficult to use than those that use manual switches.

(Means for Solving the Problems) Conventional speech recognition circuits are configured to output a signal indicating that recognition is not possible when input speech differs from pre-registered speech. The present invention takes advantage of this and includes a first counter that starts counting each time an unrecognized signal is uttered, and a signal detection circuit that outputs a signal indicating that a recognition signal indicating that the input voice has been recognized is output. a second counter that counts the number of times the unrecognized signal is generated and whose count value is cleared in response to the count signal of the first counter and the generation of the detection signal from the signal detection circuit; Detects that a signal has occurred consecutively more than a set number of times within a set time.

A first switching circuit forcibly puts the voice recognition circuit into registration mode based on this detection signal, and starts operation in response to a signal from the first switching circuit, and generates a detection signal from the signal detection circuit. a second stop generating the registration mode signal in response to the registration mode signal;
A switching circuit is provided.

(Example) The drawing is a circuit diagram of a voice recognition clock according to the present invention.

In the figure, a clock section 2 that displays the time includes an oscillator 4, a frequency dividing circuit 6, a time counter 8, a calendar counter 10, an alarm memory 12, and a coincidence circuit 1.
4・Sound generation circuit 16・Display switching circuit 18・Display section 2
has 0. Among these, the count output signals of the time counter 8, calendar counter 10, and alarm memory 12 are input to the input of the display switching circuit 18, and one of these count output signals is selected and supplied to the display section 20.

On the other hand, 22 is a microphone that detects external sounds,
It is connected to the voice recognition circuit 24. The voice recognition circuit 24 also has a registration/recognition mode switching input terminal I/O and a recognition data output terminal K that outputs recognition data indicating whether the input voice is a registered voice. Furthermore, in this embodiment, a plurality of voices are registered and recognized, and therefore the voice recognition circuit 24 uses the address data of the internal memory when storing the voice input from the microphone 22 in the registration mode. It has an address terminal K for inputting and outputting memory address data of a registered voice that matches the input voice in the recognition mode.

Of these, the registration/recognition mode switching input terminal is connected to an external switch 26 via a second switching circuit, which will be described later. When the external switch 26 is closed, the voice recognition circuit 24 is placed in the registration mode, and when the switch 26 is opened, the voice recognition circuit 24 is placed in the recognition mode. The recognition data output terminal WD is input to the decoder 28. The decoder 28 is a circuit for identifying whether the recognition data is a recognition signal for controlling a clock function or a signal that cannot be recognized, and the recognition signal is input to the display switching circuit 18 via the gate circuit 30. The display switching circuit 18 is configured to select and output one of the input count signals based on this recognition signal. The recognition signal is also input to the signal detection circuit 32. This signal detection circuit 32 is configured to output a pulse signal every time a recognition signal is input, and the pulse signal is passed through an OR gate 34 to a second pulse signal.
is supplied to the reset input R of the counter 36. The second counter 36 receives the unrecognized signal from the decoder 28 at its clock input φ, and its carry output signal is sent to the FF4 in the first switching circuit 38.
It is input to the clock input φ of 0. This FF4
The Q output of 0 is input to an I/O circuit 44 and a gate circuit 30 connected to the I/O input and K terminal of the voice recognition circuit 24 via an external switch 26 and an OR gate 42. The output is also input to an AND gate 46 within the second switching circuit 45. The AND gate 46 also has an inverted signal input from the switch 26, and the output signal is input to the reset input R of the counter 48. A signal detection circuit 32 is connected to the clock input φ of this counter 48.
This carry signal C is input to the reset input R of the FF 40.
Furthermore, the count output of the counter 48 is input to the K terminal via the I/O circuit 44. In other words, the count output of the counter 48 is the same as that of the voice recognition circuit 24.
The audio data input from the microphone 22 is stored at the memory address indicated by the data supplied to the K terminal.

Further, the first counter 50 counts a certain period of time from the generation of the unrecognized signal from the decoder 48, and the FF 52 inputs the unrecognized signal to the clock input φ, and the output of this FF 52 and the unrecognized signal are connected to each other. An input OR gate 54, a counter 56 which receives the output signal of this OR gate 54 at its reset input R, counts the signal _φ1 from the frequency divider circuit 6, and supplies the carry signal to the reset input R of the FF 52 and the OR gate 34. has.

The operation of this circuit will be explained below.

First, when registering, close the switch 26.
As a result, the voice recognition circuit 24 enters the registration mode, and the I/O port 44 can input the count output of the counter 48 to the K terminal of the voice recognition circuit 24. Thereafter, every time a voice is input from the microphone 22, a voice recognition signal is output from the WD terminal and a pulse signal is generated from the signal detection circuit 32. This pulse signal is input to the counter 48, which has been reset since the output signal of the AND gate 46 becomes L level, and increments the count value. Due to this change in the count value, the address of the memory where the next audio data input from the microphone 22 is stored is changed. In this way, a plurality of types of voices are stored one after another.

When the switch 26 is then opened, the voice recognition circuit enters the recognition mode, and the I/O port 44 no longer supplies the count output of the counter 48 to the K terminal. Then, a voice is input, and if it is the same as a previously registered voice, a recognition signal is output, and the clock function is thereby controlled, that is, the display is switched. However, if the voice is not registered in advance, an unrecognized signal is output, which causes the FF
The output of counter 52 becomes L level, and counter 56 is released from reset and starts counting. The count value of this counter 56 is cleared every time a recognition failure signal is outputted thereafter, and the count value is restarted from the beginning. If the unrecognized signal is generated before the counter 56 generates the carry signal, the second counter 36 counts the number of times this signal occurs.
When this count reaches a certain value, that is, when unrecognized failure occurs a set number of times in succession, a carry signal is generated from the second counter 36, which causes the Q output of the FF 40 to go to H level. , the output becomes L level. As a result, ORGATE 42
The output signal becomes H level and the voice recognition circuit 24
enters the registration mode, and the count output of the counter 48 can be supplied to the K terminal. Also and gate 4
The output signal of 6 becomes L level, the reset of the counter 48 is released, and the pulse signal from the signal detection circuit 32 can be counted.

In this way, the recognition mode is switched to the registration mode, and the voices inputted from now on are registered. When a predetermined number of voices are registered, the counter 48
A carry signal is generated from FF40.
The Q output of is inverted to reset counter 48 and return speech recognition circuit 24 to recognition mode.

If the unrecognizable signal occurs consecutively a set number of times within a set time in this way, voice registration is automatically redone. Furthermore, if there is no voice input for a certain period of time after the unrecognized signal is generated, a carry signal from the counter 56 causes the second counter 36 and FF to be input.
52 is cleared and returns to the original state. Furthermore, if a recognition signal is generated before the recognition failure signal is generated a set number of times in succession, the second counter 36 is cleared and the count is restarted from the beginning.

(Effects of the Invention) As described above, according to the present invention, if the voice cannot be recognized no matter how many times the voice is input, it is possible to register the voice again and register the voice that can currently be generated. This is useful if you have forgotten why the registered voice was hot, if you have a cold and cannot hear the normal voice, or conversely, if the voice you registered was the voice of a cold and you are unable to output it now, you may have to turn the switch. Easy-to-recognize voices can be registered without the hassle of operations.

[Brief explanation of the drawing]

The drawing is a circuit diagram of a voice recognition clock according to an embodiment of the present invention. 2... Clock part, 22... Microphone, 24... Voice recognition circuit, 36... Second counter, 38... First switching circuit, 45... Second switching circuit, 50...
...First counter.

Claims (1)

[Claims for Utility Model Registration] It has a clock section that displays the time, a microphone that detects external sounds, and a registration/recognition mode switching input terminal, and when in the registration mode, the voice from the microphone is registered and the recognition mode a voice recognition circuit that outputs a recognition signal for controlling the function of the clock section when the voice from the microphone is the same as the previously registered voice, and outputs an unrecognizable signal when the voice is different; , an external switch that is connected to the registration/recognition mode switching input terminal of the voice recognition circuit and outputs a signal for switching between the recognition mode and the registration mode by external operation; a first counter that starts counting the clock signal from the clock section every time a recognition signal from the voice recognition circuit is generated; a signal detection circuit that generates a detection signal every time a recognition signal from the voice recognition circuit is generated; a second counter that counts the number of times a disable signal is generated and whose count value is cleared in response to the generation of a detection signal from the signal detection circuit and a count signal from the first counter; a first switching circuit that forcibly outputs a registration mode signal to the registration/recognition mode switching input terminal of the voice recognition circuit when the count value of the counter reaches a set value; a second switching circuit that operates in response to the generation of the registration mode signal and stops generation of the registration mode signal from the switching circuit in response to the detection signal from the signal detection circuit. .