JPH056554Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a watch with a voice recognition function, and in particular allows the snooze time to be arbitrarily set by inputting voices corresponding to multiple units of time. Regarding what can be done.

(b) Prior art Conventionally, Japanese Patent Application Laid-Open No. 60-25487 and
As disclosed in Japanese Patent No. 56-143988, a watch has been proposed in which a snooze function can be activated by generating a sound during alarm notification.

In this way, instead of a manual snooze switch,
In order to perform a snooze operation by voice, a word for starting a snooze operation is registered in advance in the voice recognition circuit, and the snooze operation is started when this word is input by voice.

Furthermore, in recent years, it has been proposed to register a word representing the snooze pause time and input this word by voice to cause the snooze to pause for the time corresponding to the word.

(c) Problems to be solved by the invention When changing the snooze pause time using voice as in the above conventional example, the number of times that can be changed is extremely limited with current voice recognition ICs.

This is because the number of spoken words that can be registered in the speech recognition IC is fixed.

In this way, with conventional watches, it was possible to set the snooze pause time only at the time corresponding to each registered voice, so the number of variable times was fixed, making it difficult to use. It was not possible to respond flexibly to people's requests.

(d) Means for solving the problem The purpose of the present invention is to arbitrarily and freely vary the snooze pause time without changing the configuration of the current speech recognition IC, which has a fixed number of recognizable words. Our goal is to provide a voice recognition watch with a snooze function.

In order to solve the above issues and achieve the objectives,
The voice recognition clock with a snooze function of the present invention recognizes voices corresponding to multiple predetermined unit times and adds or subtracts the unit times to obtain the snooze time. If the snooze time is not available, the snooze time is set at a predetermined time.

Therefore, the voice recognition clock with snooze function of the present invention includes a snooze circuit that temporarily stops the alarm notification function, and a snooze time signal that adds or subtracts a predetermined number of snooze time signals according to the unit time supported by the voice and outputs the result. A setting circuit, a snooze timer circuit that stops the snooze operation when the time corresponding to the snooze time signal is counted, and a snooze timer circuit that sets the snooze time signal to a predetermined value when the input voice cannot be recognized. A snooze time appropriate circuit is provided.

(e) Embodiment First, an overview of the operation of the characteristic parts of a voice recognition watch with a snooze function according to an embodiment of the present invention will be explained.

When the user inputs "snooze" by voice during alarm notification, the watch in this embodiment recognizes this and temporarily stops alarm notification.

After that, if you input a preset voice such as "1 minute", "2 minutes", "4 minutes", "8 minutes", etc., the snooze time corresponding to each voice will be added, and then "1 minute" will be added again. , "2 minutes," etc., when the same voice as the voice input once is input, the snooze time corresponding to that voice is subtracted, and the final value of the addition/subtraction is set as the snooze time.

For example, if you input audio such as "1 minute", "2 minutes", or "4 minutes", the snooze time will be 7 minutes, which is the snooze time corresponding to this audio, and then "2 minutes".
When the snooze time corresponding to this voice is input as "minutes", the snooze time is set to 5 minutes, which is obtained by subtracting the snooze time from the 7 minutes.

Furthermore, if the input voice cannot be recognized, a predetermined snooze time (4 minutes in this embodiment) is set.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing a circuit configuration of a voice recognition watch with a snooze function according to an embodiment of the present invention.

Reference numeral 2 designates a clock circuit including an oscillation circuit 4, a frequency divider circuit 6 which divides the frequency of its output signal as appropriate and outputs a clock signal, a clock circuit 8 which measures time based on the output signal, and displays the output signal. It is composed of a decoder driver 10 that converts into a drive signal, and a display section 12 that is driven by the display drive signal and displays the time.

14 is an alarm circuit, which includes an alarm setting circuit 16 for setting and storing an alarm time, a coincidence detection circuit 18 for inputting an output signal indicating the alarm time and a time signal from the clock circuit 8, and a voice command circuit to be described later. A flip-flop (hereinafter abbreviated as EF) 20 inputs an alarm-on command signal and an alarm-off command signal B ₆ from the alarm to the set input S and reset input R, respectively, and the signal from the output Q and the coincidence detection circuit 18. an AND gate 22 which inputs a signal, an FF 24 which inputs its output signal and an alarm off signal _B6 to a set input S and a reset input R, a signal _A1 from its output Q, and a snooze signal from a snooze circuit described later. The AND gate 26 inputs the signal C and outputs the alarm operation signal _A2 .

Reference numeral 28 denotes a sound generation circuit which receives the alarm operation signal _A2 and generates an alarm sound.

30 is an audio detection circuit that detects external audio and outputs an audio signal.

32 is a voice command circuit, and voice detection circuit 30
A voice recognition circuit 34 which inputs a voice signal from a voice and recognizes it as the same as one of pre-registered voice data, outputs a 4-bit signal corresponding to the voice data from outputs _W1 to _W4 ; A decoder 36 that inputs a 4-bit output signal and outputs signals from a plurality of output terminals according to its state, and a one-shot multivibrator (hereinafter abbreviated as OS) that inputs signals from each of the output terminals.
38 to 52, output signals of OS38 to 50, and OS5
an OR gate 54 that inputs all output signals of 2;
56, and a delay circuit 58 which inputs the output signal of the OR gate 56 and applies the signal to the standby input STBY of the speech recognition circuit 34.
The audio circuit 34 in the audio command circuit 32 has various sounds such as "alarm on", "alarm off", "snooze", "1 minute", "2 minutes", "4 minutes", and "8 minutes". Data is registered in advance. The voice recognition circuit 34 is also set to output a predetermined signal indicating non-recognition when the input voice cannot be recognized. In addition, the OS in the voice command circuit 32 in this embodiment
The output signals from 38 to 52 are alarm on, alarm off, snooze, 1 minute, 2 minutes, and 4, respectively.
It serves as a command signal indicating minutes, eight minutes, and non-recognition.

60 is a snooze circuit, and alarm circuit 14
and an AND gate 62 that inputs the signal A ₁ from the voice command circuit 32 and the snooze command signal B ₁ from the voice command circuit 32;
The output signal and a signal E from a snooze clock circuit, which will be described later, are input to set input S and reset input R, respectively.
and an FF 64 which inputs a snooze signal C and outputs a snooze signal C from its output.

66 is a snooze time setting circuit, which includes an OR gate 68 that inputs signals B ₂ , B ₃ , and B ₅ from the voice command circuit 32, and the output signal and the voice command circuit 32.
An OR gate 70 inputs the signal B ₄ from the 4-bit clock, a NAND gate 72 inputs its output signal to one input terminal and outputs the signal D ₁ , and clocks the output signal D ₁ and the snooze signal C from the snooze circuit 60, respectively. φ and set input S and output Q
FF 74 applies the signal D ₂ outputted from the NAND gate 72 to the other input terminal, and the output signal D ₂ is inverted and inputted to one input terminal, and the voice command circuit 22
an AND gate 76 that inputs the signal B ₄ from the FF 74 to the other input terminal, and an AND gate 78 that inputs the signal D ₂ from the FF 74 and the output signal of the OR gate 68;
FFs 80, 82, and 86 input signals B ₂ , B ₃ , and B ₅ from the voice command circuit 32 to each clock input φ, and input a signal F ₂ from a snooze time appropriate circuit described later to each reset input R; , and an FF 84 which inputs the output signals D ₃ and D ₄ of the AND gates 76 and 78 to the clock input φ and the reset input R, respectively, and inputs the signal F ₂ from the snooze time appropriate circuit to the set input S. . Signals output from each output Q of these FF80-86
_D5 to _D8 are 4-bit signals indicating snooze time.

88 is a snooze timer circuit, which includes a counter 90 which inputs the snooze signal C from the snooze circuit 60 to the reset input R and inputs the clock signal φa to the clock input φ, a signal indicating the count value, and a snooze time setting circuit 66. Signal from D ₅ ~
If input D ₈ and their contents match, signal E
It is composed of a coincidence detection circuit 92 that outputs .

94 is a snooze time appropriate circuit, which converts the snooze signal C from the snooze circuit 60 to the inverter 96.
to one input terminal via the voice command circuit 32.
AND gate 98 which inputs the non-recognized signal B ₇ from the output terminal to the other input terminal, FF 100 which inputs its output signal and the snooze signal C to the set input S and reset input R, respectively, and the signal F ₁ from its output Q. and an OR gate 102 which inputs the snooze signal C and outputs the signal _F2 .

Next, the operation of the circuit having the above configuration will be explained based on the time chart shown in FIG.

When the time set in the alarm setting circuit 16 arrives, the coincidence detection circuit 18 detects this and sets its output signal to H level. At this time, if the FF 20 is already in the set state due to the pulse generated in the alarm-on command signal from the voice command circuit 32, the AND gate 22 is in the open state, and the H level signal from the coincidence detection circuit 18 is output. of
Apply to set input S of FF24. The FF 24 enters the set state in response to this signal, and sets its output signal _A1 to H level. When this signal A ₁ becomes H level, this signal A ₁ is generated as the output signal A ₂ of the AND gate 26 which is normally in an open state because the snooze signal C is at H level. This signal A ₂
When the signal becomes H level, the sound generation circuit 2 responds to this.
8 generates an alarm sound.

If the voice "snooze" is input from the voice detection circuit 30 while in the alarm notification state as described above, the voice recognition circuit 34 recognizes this voice and responds to the voice "snooze" from its outputs W ₁ to _{W 4} . Outputs a code signal. The decoder 36 applies an H level signal to the OS 42 in response to the signal from the voice recognition circuit 34. OS 42 responds to this signal by pulsing its output signal _B1 . The pulse generated in this signal _B1 is generated at the output of the AND gate 62 in the snooze circuit 60, which is already in an open state, and this signal is passed to the set input S.
The FF 64 input to the FF 64 enters the set state. This FF
When the alarm 64 enters the set state, the snooze signal C from its output goes to the L level, which causes the AND gate 26 in the alarm circuit 14 to close. Therefore, the alarm operation signal _A2 outputted by the AND gate 26 becomes L level, and the sound generation circuit 28 stops generating the alarm sound. Note that when a pulse is output from any of the OSs 38 to 52, the voice recognition circuit 34 inputs the pulse to the standby input STBY via the OR gates 54 and 56 and the delay circuit 58, and clears the output. There is.

Following this, when the voice "4 minutes" is input, the voice recognition circuit 34 recognizes this voice and outputs a code signal corresponding to this voice from outputs _W1 to _W4 . In response to this, the decoder 36 which receives this signal applies an H level signal to the OS 48 which outputs a unit time command signal _B4 indicating 4 minutes. Therefore, the OS 48 pulses its output signal to _B4 .

In this example, the normal snooze time is 4
Since the snooze time setting circuit 66 is set to the minute, the FF 84 in the snooze time setting circuit 66 is in the set state in the initial state, and its output signal _D7 is at the H level. Therefore, the snooze time signals D ₅ to _{D 8} are
It is now ``0100'' which indicates ``4'' in binary. Therefore, in this state, even if "4 minutes" is input by voice and a pulse is generated in the signal _B4 , the snooze time of 4 minutes has already been set, so this pulse is generated by the AND gate 76 in the closed state. It is prohibited from being applied to the clock input φ of FF84.

On the other hand, the pulse generated in this signal B ₄ is also applied to the NAND gate 72 via the OR gate 70 . Then, the output signal of this NAND gate 72
A pulse that is an inversion of the pulse of signal B ₄ is generated at D ₁ , and FF 7 is activated in synchronization with the rising edge of this pulse.
4 sets the output signal _D2 , which is normally at H level, to L level. When this signal _D2 goes to L level, the AND gate 76 which inverts it and inputs it becomes open. As a result, if a further pulse occurs on signal B ₄ , this pulse is passed through AND gate 76.
It will be applied to the clock input φ of the FF86.

As mentioned above, when the output signals _D5 to _D8 of the snooze time setting circuit 66 indicate "4 minutes",
Furthermore, when "8 minutes" is input by voice, the voice recognition circuit 34 recognizes this in the same manner as in the operation described above, and the decoder 36 applies an H level signal to the OS 50.
OS 50 responds to this signal by pulsing its output signal _B5 . The pulse generated in this signal _B5 is transmitted to the FF86 in the snooze time setting circuit 66.
The FF 86 sets its output signal D ₈ to H level in synchronization with the rising edge of this pulse.

At this stage, signals D ₇ and D ₈ among the signals D ₅ to D ₈ are at H level, indicating "12 minutes" which is 8 minutes added to 4 minutes.

After that, if you input "4 minutes" again, the OS48 will output the output signal in the same way as described above.
Generate a pulse on B ₄ . At this time, since the AND gate 76 is already in the open state as described above, the pulse generated in the signal B ₄ is now generated in the output signal D ₃ of the AND gate 76 and is applied to the clock input φ of the FF 84. Ru. For this reason, FF8
4 sets its output signal _D7 to L level in synchronization with the rising edge of this pulse.

As a result, only the signal _D8 among _D5 to _D8 indicating the snooze time is at H level, indicating "8 minutes".

A coincidence detection circuit 92 receives these signals _D5 to _D8 .
compares the count value of the counter 90 that starts counting at the start of snooze with the signals _D5 to _D8 , and when they match, that is, the count value is "8 minutes".
When this happens, a pulse is generated in the output signal E.

The pulse generated in this signal E is applied to the reset input R of the FF 64 in the snooze circuit 60,
This FF64 enters a reset state. This results in
The output signal C of the FF64 becomes H level. When this signal C becomes H level, the AND gate 26 in the alarm circuit 14 is opened again, and its output signal _A2 becomes H level. Therefore, the sound generation circuit 28 generates the alarm sound again.

Further, when the signal C becomes H level, the counter 90 in the snooze timer circuit 88 is reset, and the FF 74 in the snooze time setting circuit 66 is set. Therefore, the signal D ₂ becomes H level again, and the AND gates 76 and 78 are closed and opened, respectively. Further, the H level signal C is generated as the signal F ₂ via the OR gate 102 in the snooze time appropriate circuit 94. This signal F ₂ is FF80,8
Since it is applied to the reset input R of F2, 86 and the set input S of FF84, when this signal _F2 becomes H level, the FF86 is reset and the FF84 is reset.
84 is set. As a result, only the signal _D7 becomes H level again, and the snooze time is set to "4 minutes".

When returning to such an alarm notification state, if you input the word "snooze" again by voice, a pulse is generated in the snooze command signal _B1 from the voice command circuit 32, similar to the operation described above, and this pulse activates the snooze circuit. FF 64 in FF 60 is set and the snooze signal C becomes L level. For this reason,
The AND gate 26 in the alarm circuit 14 is closed, the alarm operation signal _A2 becomes L level, and the alarm notification is stopped.

Here, when "1 minute" is input by voice, the voice recognition circuit 34 recognizes this, and the decoder 36 applies an H level signal to the OS 44 in response to the signal from the voice recognition circuit 34. This causes OS 44 to generate a pulse on its output signal _B2 , which pulse is applied to the clock input φ of FF 80. As a result, the FF 80 sets its output signal _D5 to H level in synchronization with the rise of the pulse of the signal _B2 .
Also, at this time, the pulse generated in signal B ₂ is
A signal D ₄ is generated via OR gate 68 and AND gate 78 which is open. this signal
The pulse generated at _D4 is applied to the reset input R of FF 84, and FF 84 is reset.

As a result, the signal D ₇ becomes L level, and in its place, the signal D ₅ becomes H level, so that the snooze time "1 minute" is set.

Incidentally, the pulse generated in this signal _B2 is also applied to the NAND gate 72 via the OR gate 68, and is applied to the NAND gate 72 in the same manner as described above.
The output signal D _{of 1} is inverted and generated, which causes the FF
74 sets its output signal _D2 to L level. As a result, AND gate 78 is brought into a closed state, and AND gate 76 is brought into an open state.

Subsequently, when "2 minutes" is input by voice, the voice recognition circuit 34 recognizes this in the same way as in the operation described above, and furthermore, the decoder 36 responds to the output of the voice recognition circuit 34 and sends an H level signal to the OS 46. Apply. In response, OS46 outputs its output signal B ₃
A pulse is generated, and this pulse is applied to the clock input φ of the FF 82. In synchronization with the rise of this pulse, FF8
2 sets its output signal _D6 to H level.

As a result, the signals D ₅ and D ₆ become H level, and "2 minutes" is added to the snooze time "1 minute", resulting in "3 minutes".
You will now be able to set the minute.

If further voice is input here, and the input voice is other than the voice registered in the voice recognition circuit 34, or if the voice recognition circuit 34 cannot recognize it due to external conditions, A signal at the time of non-recognition is generated at the outputs W ₁ to _{W 2} of the speech recognition circuit 34 . In response to this signal, the decoder 36 applies an H level signal to the OS 52,
OS 52 pulses its output signal _B7 .

This pulse generated in signal B ₇ is applied to AND gate 98 in snooze time appropriate circuit 94 . Since the snooze operation is currently in progress, the snooze signal C is at L level, and therefore the AND gate 98 which inputs this signal C via the inverter 96 is in an open state. Therefore, signal B ₇
The pulse generated at is generated at the output of this AND gate 98 and applied to the set input S of the FF 100. As a result, FF100 enters the set state,
The output signal _F1 becomes H level. This H level signal F ₁ is passed through the OR gate 102 to the signal F ₂
It occurred in FF80, 82, 86 as mentioned above.
It is applied to the reset input R of the FF84 and the set input S of the FF84. Therefore, the FFs 80 and 82, which were already in the set state, are reset, and the FF 84 is reset in their place.

As a result, only signal _D7 becomes H level again.
You will now be in a state where you can set the snooze time to ``4 minutes.''

In this state, the snooze time appropriate circuit 94
It will be maintained until FF100 is reset, so
For example, in this state, even if "8 minutes" is input by voice and a pulse is generated in the signal _B5 , the FF 86 will maintain the reset state by the signal _F2 .

Thereafter, in the same manner as described above, the output signal E of the coincidence detection circuit 92 in the snooze clock circuit 88 is
A pulse is generated in the snooze circuit 60 again.
When the FF 64 is reset and alarm notification is started, the snooze time appropriate circuit 94 is reset by the snooze signal C which has become H level at this time and returns to the initial state.

In this way, the clock in this embodiment can set the snooze time by adding or subtracting the snooze time by inputting a pre-registered voice, and if the input voice cannot be recognized,
It is configured to set a predetermined snooze time and then maintain the set snooze time regardless of subsequent input audio until alarm notification is resumed.

In addition, by voice inputting "alarm off", a pulse is generated in the output signal B ₆ of the OS 40, and the pulse of this signal B ₆ turns off the FF in the alarm circuit 14.
20 and 24 are both reset, the signal _A1 goes to L level, and the AND gate 26 is closed, so that the notification stops ringing.

(f) Effects of the invention According to the invention, the desired snooze time can be set by adding and subtracting each unit time simply by inputting the audio corresponding to the desired unit time, and the number of words that can be recognized is determined. Current voice recognition ICs
You can freely change the snooze pause time using . In particular, since the snooze pause time is variable depending on the audio input during the snooze operation,
It is possible to prevent voice recognition from deteriorating due to the alarm sound, and to make snooze-related settings and changes on the spot during the snooze operation depending on the usage situation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of a voice recognition clock with a snooze function according to an embodiment of the present invention, and FIG. 2 is a time chart. 2...Clock circuit, 14...Alarm circuit, 28
...Audio circuit, 30...Audio detection circuit, 32...
Voice command circuit, 60... Snooze circuit, 66...
Snooze time setting circuit, 88...Snooze timing circuit, 94...Snooze time appropriate circuit.

Claims (1)

[Claims for Utility Model Registration] A clock circuit that clocks a reference signal and outputs a time signal; an alarm circuit that outputs an alarm operation signal when an arbitrarily settable alarm time signal matches the time signal; a sound generation circuit that notifies an alarm sound in response to the output of the alarm operation signal; a sound detection circuit that detects an external sound and outputs a sound signal; and a piece of sound data in which the sound signal is registered in advance.
a voice command circuit that outputs a command signal corresponding to the registered voice data when the voice signal is recognized as being the same as one of the registered voice data, and outputs a non-recognition signal when the voice signal is recognized as not being the same as all the registered voice data; A watch comprising: a snooze circuit that outputs a snooze signal for inhibiting the output of the alarm operation signal in response to the output of the snooze command signal from the voice command circuit; It is possible to input the unit time command signal from
a snooze time setting circuit that adds or subtracts a predetermined number of bits of the snooze time signal according to each input unit time command signal; a snooze timing circuit that outputs a snooze end signal that stops outputting the snooze signal; and a snooze time appropriate circuit that maintains the snooze time signal at a predetermined value in response to the output of the non-recognition signal from the voice command circuit. A voice recognition clock with a snooze function characterized by the following.