JPH0214672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a clock that notifies the time by voice, and more particularly, to a clock that can recognize the time even when the surroundings are noisy and it is hard to hear clearly.

(Prior art) As shown in Japanese Patent Application Laid-Open No. 56-49980,
A device that audibly announces the time indicated by a clock has been proposed, and this type of clock allows the time to be known only by hearing when the indicated time is difficult to read, such as at night. It is widely available as

(Problems to be Solved by the Invention) However, since such audio clocks are recognized by hearing, they are very susceptible to external noise and quickly become difficult to hear. Moreover, unlike changes in illuminance, external noise often increases suddenly and suddenly, and when such external noise occurs, it often becomes impossible to recognize the time.

(Means for Solving the Problems) In order to solve the above-mentioned conventional problems, the present invention uses time numerals and audio data in time units such as "ji" and "hun" to notify the time audibly. In the stored voice ROM, voice data is also stored to the effect that the device should wait a little longer for the voice notification of the time. The voice clock also includes a noise detection circuit that detects external noise, and this noise detection circuit allows the time to be announced audibly when the external noise is low and does not interfere with recognition of the time voice, and when the external noise is large. If the time voice cannot be recognized sufficiently, the voice notification will give a voice notification asking you to wait a little while, and then when the external noise has decreased, the time will be announced anew by voice ROM.
It has a selection circuit that selects the audio data read out from the system, and a restart circuit that notifies the time when the noise has decreased.

According to this method, the time is announced after the noise has decreased, making it possible to recognize the time, but the notification is delayed from when the user actually wants to know the time. . Therefore,
The present invention further includes a counter that starts counting from the time when the user operates an external switch to check the time, and when the time audio is announced late due to loud noise, the counter starts counting when the user operates an external switch to check the time. The count signal of the counter is supplied to the aforementioned selection circuit in order to notify the count time of the counter by voice.

(Embodiment) FIG. 1 is a block diagram of an audio clock according to an embodiment of the present invention.

A high frequency signal from a reference signal generator 10 including a crystal oscillator, etc. is converted into a desired frequency-divided pulse train by a frequency dividing circuit 12, and minute pulses with a period of 60 seconds are supplied to a minute counter 16. Minute counter 16 comprises a sexagesimal counter and supplies its output, the hour pulse, to hour counter 18, which comprises a decimal counter.

Minute counter 1 is used to notify the designated time by voice.
6 and the count value of the hour counter 18 are supplied to the selection circuit 20, and at the same time, the selection circuit 20 is supplied with a code signal for reading out the sound "Hun" or "Ji" from the audio ROM, which will be described later.
It is supplied from the ROM 22 and the "Hun" code ROM 24.

Furthermore, the selection circuit 20 includes a standby code ROM 28 which stores a code signal for reading out data for notifying the voice "Scosiomacchikudasai" from the audio ROM 26, and a standby code ROM 28 which stores a code signal for reading out data for notifying the voice "Scottish machikudasai" when the external time signal switch 30 is operated. The elapsed time counter 32 starts counting from , and when notifying the elapsed time by voice, data is input from the modifier code ROM 34 in which a code signal for reading data is stored to notify, for example, "Fun Kei Kashima Shita". ing.

The selection circuit 20 selectively outputs any one of these data and supplies it to the audio signal generation circuit 38. This selection circuit 20 includes a standby code ROM 28, an hour counter 18, and a "di" code.
ROM22, minute counter 16, "Hun" code
The ROM 24, the elapsed time counter 32, and the modification code ROM 34 are configured to be selectively output in this order, but which output is to be started is controlled by the connected external noise detection circuit 36. That is, when the external noise detection circuit 36 detects that the external noise is small, it selects from the count output signal of the hour counter 18, and when the external noise is large, it selects from the code signal from the standby code ROM 28. The selected output signal is supplied to the audio signal generation circuit 38. The audio signal generation circuit 38 is
Desired audio data is read from the audio ROM 26 and output as an audio signal, which is input to the sound generation circuit 40.

Further, the audio signal generation circuit 38 is operated by an operation start circuit 42. This operation start circuit 42
starts operation by operating the external switch 30, and if the noise detection circuit 36 detects that the external noise is small, the "Hun" code ROM2 is activated.
The operation is stopped when the audio read out in step 4 ends. If the external noise is large, the operation is stopped when the sound read by the standby code ROM 28 ends. After this, when the external noise becomes smaller, the restart circuit 4
4, the operation start circuit 42 operates the audio signal generation circuit 38 again, and then the selection circuit 20 selectively outputs from the hour counter 18 to the modification code ROM 34, and this selection output signal causes the audio signal generation circuit 38 to: Current time and elapsed time counter 32
Generates the elapsed time counted by and the associated modifier.

FIG. 2 is a detailed circuit diagram of the selection circuit 20, audio signal generation circuit 38, sound generation circuit 40, operation start circuit 42, and restart circuit 44 in FIG. 1.

The selection circuit 20 includes an hour counter 18, a minute counter 16, a standby code ROM 28, and a "ji" code ROM.
22, a digital multiplexer 46 into which signals from the "Hun" code ROM 24, the elapsed time counter 32, and the modifier code ROM 34 are input. The selection control input of this digital multiplexer 46 includes the outputs 48a to 4 of the decimal counter 48.
8j is input, and when the outputs 48a to 48j become "H" in that order, the standby code ROM2
8, hour counter 18, "ji" code ROM 22,
Minute counter 16, "Hun" code ROM 24, elapsed time counter 32 and modifier code ROM 3
They are selectively output in the order of 4.

The audio signal generation circuit 38 includes a start address designation ROM 50 that designates a start address based on data from the digital multiplexer 46, and an end address designation ROM that designates an end address.
52, an address counter 54 and a digital converter 56. End address counter 5
4 is a circuit that sequentially starts counting from the start address and reads necessary audio data from the audio ROM 26. Also, the digital comparator 56
is a circuit that detects whether the count value of the address counter 54 matches the end address. The D-A converter 58 is connected to the audio ROM 26.
The low-pass filter 60 is a circuit that converts digital audio data from the D-A into an analog signal.
This circuit removes unnecessary harmonic components from the analog signal from the converter 58 and supplies it to the sound generation circuit 40 consisting of an amplifier 62 and a speaker 64.

On the other hand, the audio signal generation circuit 38 starts operating when an address pulse is input from the operation start circuit 42 to the address counter 54.
This address pulse consists of a constant period signal φ ₁ from the frequency divider circuit 12 via an AND gate 66,
Opening and closing of the AND gate 66 is controlled by the Q output of the FF 68. This FF68 reset input R
The output of the OR gate 70 via the one-shot multivibrator 69 is input to the OR gate 70, and the final output 48j of the decimal counter 48 and the output 48 via the AND gate 72 are input to the OR gate 70.
b, and output 48h via AND gate 74
is inputting.

On the other hand, the output signal from the OR gate 76 in the selection circuit 20 is input to the set input S of the FF 68. First, the output signal of the AND gate 78 in the restart circuit 44 is input to the OR gate 76, and the AND gate 78 receives the Q output of the FF 88 and the noise via the inverter 82 and one-shot multivibrator 81 in the selection circuit 20. The output signal of the detection circuit 36 is input.

OR gate 76 has other AND gates 84, 8
6 output signals are input. This AND gate 84 also includes a one-shot multivibrator 8.
8 is connected to the external switch 30, and an output signal from the noise detection circuit 36 is input to the AND gate 84, and an output signal from the noise detection circuit 36 via an inverter 82 is input to the AND gate 86.
The output signal of the external switch 30 via this one-shot multivibrator 88 is sent to the decimal counter 4.
It is also input to the reset input R of No.8.

On the other hand, the output signal of the AND gate 84 is
It is also input to the set input S of 0 and 90. this house
The reset input R of FF90 has the same function as FF80.
The output 48j of the decimal counter 48 is input, and its Q
The output is input to the above-mentioned AND gate 72, and the Q output is input to the AND gate 74 and the elapsed time counter 32.
input to the reset input R of the

Further, the output signal of the AND gate 86 via the delay circuit 92 is sent to the decimal counter 48 clock input φ via the OR gate 94 together with the coincidence signal of the digital comparator 56 in the audio signal generating circuit 38.
input as a step signal.

The operation of this circuit will be explained below using time charts shown in FIGS. 3 and 4.

FIG. 3 is a time chart showing the operation when external noise is small. At this time, the noise detection circuit 36
The output signal of the inverter 82 is "L", and since the output signal of the inverter 82 is "H" at this time, the AND gate 84 is closed.

When the external switch 30 is operated in this state, a positive single pulse is generated from the one-shot multivibrator 88, and this pulse is transmitted to the decimal counter 48.
is first cleared, and then delayed through the AND gate 86 and the delay circuit 92, and the decimal counter 48
clock input φ and FF68 set input S. As a result, the Q output signal of the FF 68 becomes "H", and the AND gate 66 is opened to supply an address pulse to the address counter 54. Also, the decimal counter 48 is incremented by +1, and the output 48
b becomes "H" and the digital multiplexer 46
selects the count output of the hour counter 18 and outputs it to the audio signal generation circuit 38. As a result, both the start address and end address, which are the selection signals from the digital multiplexer 46, are specified.
It is stored in the ROMs 50 and 52. This selection signal is stored in the order of the output signals from the digital multiplexer 46. For example, in the case of the indicated time "12:35", the digital multiplexer 46 first stores the number in the 10th place of the hour counter 18, that is, "JYU". is stored in the start address and end address designating ROMs 50 and 52 as selection signals. As the start address of the specified ROM 50, the start address of the audio signal "JIU" is selected from the audio ROM 26 via the address counter 54, and this audio signal is accessed and converted into an analog signal by the D-A converter 58. Unnecessary harmonic components are removed by a low-pass filter 60 and output. Access to the audio ROM 26 is performed by counting the address counter 54 until the current address matches the end address. For this purpose, the current address is sequentially compared with the end address of the end addressing ROM 52 by a digital comparator 56. Then, when the current address and the end address match, that is, the reading of the audio signal "JYU" is completed, the process moves to the next audio signal reading step.

At this time, the coincidence signal from the digital comparator 56 is input to the clock input φ of the decimal counter 48, and the count value is incremented by +1. This happens when
The output 48c of the decimal counter 48 becomes "H",
The digital multiplexer 46 selects the first signal of the hour counter 18, that is, "D", and supplies it to the audio signal generation circuit 38. Similarly, "J",
The audio signals "san", "jiu", "go", and "hun" are read out by each of the output signals 48d to 48g becoming "H" in sequence.

When "Hun" is read out and an audio notification is made, the decimal counter 48 is further incremented by +1 by the coincidence signal from the digital comparator 56, and the output is 48h.
becomes “H” and is input to the AND gate 74.
At this time, since the "H" output signal from the FF 90 is input to the AND gate 74, its output signal becomes "H". This "H" signal is input to the reset input R of the FF 68 via the OR gate 70, and the Q output signal is set to "L", thereby closing the AND gate 66. As a result, no address pulse is input to the address counter 54, and the audio notification is stopped.

Due to this operation, the sound generation circuit 40 generates the sound "Jiyuunijisanjiyugofun".

Next, the voice notification operation when the external noise is large will be explained using the time chart shown in FIG.

In this state, the output signal of the noise detection circuit 36 is "H", so the AND gate 84 is opened and the AND gate 86 is closed. If the external switch is operated here, the single pulse from the one-shot multivibrator 88 will cause the
The count value of the advance counter 48 is cleared and the output 48a becomes "H". However, this pulse is now passed through AND gate 84 to FF90, 68, 8.
0 set input S, and its Q output is “H”.
shall be. When the Q output of FF90 becomes "H", the AND gate 72 is opened and the output becomes "L".
As a result, the elapsed time counter 32 is released from reset and starts counting. Also FF
When the Q output of 68 becomes "H", the audio signal generating circuit 38 starts operating as before. However, at this time, the code signal of the standby code ROM 28 is being output to the audio signal generating circuit 38.
For this reason, the sound generation circuit 40 produces a sound such as, for example, "Skosio machikudasai."

When this audio notification ends, the decimal counter 4 is activated by the coincidence signal from the digital comparator 56.
8 is incremented by +1, and the output 48b becomes "H".
This "H" signal is converted into a single pulse signal via an AND gate 72 and an OR gate 70.
Reset only FF68. As a result, the audio signal stops. However, since FFs 80 and 90 are not reset, this Q output remains at "H".

Thereafter, when the external noise becomes smaller and the output signal of the noise detection circuit 36 becomes "L", the one-shot multivibrator 81 generates a single pulse.
This single pulse is AND gate 78, OR gate 7
6 to the set input S of the FF 68, and the audio signal generating circuit 38 is operated again. At this time 10
The output 48b of the forward counter 48 has become "H", and thereby the digital multiplexer 46 selects the output data of the 10th position of the hour counter 18. Therefore, the audio signal generation circuit 38 generates the audio signal for the 10th place of the hour, as in the case described above, and then the 1st place of the hour, "J", the 10th place of the minute, the 1st place of the minute, and "Hun". ”
and generate an audio signal. If the time when the switch 30 is pressed is 12:35, and the noise decreases two minutes later, the sound generation circuit 40 generates the sound "Jiyuunijisanjiyuunanafun."

When this audio notification ends, the output of the output 48h becomes "H", but at this time, the AND gate 7
Since 4 is closed, FF68 is not reset,
The audio signal generation circuit 38 continues to operate, and the digital multiplexer 46 selects the count time signal of the elapsed time counter 32. Therefore, the audio signal generation circuit 38 notifies the elapsed time, that is, "d". When this notification ends, the output 48i becomes "H" and the code of the modifier code ROM 34 is selected this time. Therefore, the audio signal generation circuit 38 generates an audio signal of a modifier, for example, "funkeikashimashita."

After this, when the output 48j becomes "H", FF6
8, 80, and 90 to end the voice notification.

Therefore, for example, if you operate the external switch 30 when the time is 12:35 and the external noise is loud,
After announcing "Scosiomacchikudasai",
For example, if the external noise decreases after two minutes, the user will be notified that the external noise has decreased after two minutes.

(Effects of the Invention) According to the present invention, when it is difficult to read a complicated time due to loud external noise, a relatively easy-to-understand voice notification asking to wait a little longer is sent instead of an audio notification of the time. Then, the time is notified when the external noise decreases, so even if the external noise is loud, the time can be recognized once the external noise subsides. In addition, since the time that occurred in this way has passed the time that the user wanted to know, the user will be notified by voice how many minutes have passed since the user tried to notify the time after the time is announced, so the user will not be able to know the actual time. You can even track the time it took place.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a voice clock according to an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of the main part of FIG. 1. 3 and 4 are time charts showing the operation of FIG. 2. 16...minute counter, 18...hour counter, 2
0...Selection circuit, 28...Standby code ROM, 3
2... Elapsed time counter, 36... Noise detection circuit, 38... Sound signal generation circuit, 40... Sound generation circuit, 42... Operation start circuit, 44... Restart circuit.

Claims (1)

[Claims] 1. A counter that measures time, an audio ROM that stores audio data for audio notification of time and time units, and reads desired data from the audio ROM based on the time signal from the counter and outputs an audio signal. In a watch with an audio notification function, the watch has an audio signal generation circuit, a sound generation circuit that generates a sound based on an output signal from the audio signal generation circuit, and an operation start circuit that starts the operation of the audio signal generation circuit by operating an external switch. , a code ROM for storing audio data different from the time audio in the audio ROM, and reading out the different audio data; an elapsed time counter that starts counting when the external switch is operated; and an external noise counter. a noise detection circuit to detect;
When the noise during operation of the external switch is below a certain value, the noise detection circuit selects the time signal, and when it is above a certain value, selects the output signal from the code ROM and supplies it to the audio signal generation circuit. a selection circuit that selects the code; and the selection circuit selects the code.
After selecting the output signal of the ROM, when the noise detection circuit detects that the noise has become below a certain value, it causes the selection circuit to select the output signal of the elapsed time counter following the time signal, and then restarts the operation start circuit. a restart circuit that operates the
A watch with an audio notification function, which is characterized by the addition of.