JPH0346792B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timepiece equipped with a sound generating device, and particularly to a timepiece that notifies the time and other information during timekeeping.

In general, when timing a watch, especially an all-electronic watch that uses an optical display, there is a problem in that if it is done at high speed, the display cannot follow it, making it impossible to confirm the timing. Also, as a matter of course, one must visually concentrate on the display while adjusting the timing. If one is distracted by surrounding circumstances or has to set the time in a dimly lit place, the desired time setting time may end up being missed.

SUMMARY OF THE INVENTION Therefore, the present invention provides a timepiece equipped with a sound generating device that notifies the user of the elapsed time during time adjustment by means of sound so that the time of time adjustment can be confirmed.

An embodiment of the present invention will be described below based on the drawings. 1 is a crystal oscillator, 2 is a frequency divider, and 3 is a pulse generation circuit that generates pulses in response to manual rotation operation. 4 is a timer, which generates a pulse output when counting, for example, 5 seconds. 5 to 8 are counters for measuring one digit of minutes, two digits of minutes, hour, and morning and afternoon, respectively. Numerals 9 to 12 are latch circuits that temporarily store the outputs of the respective counters, and 13 is a speech synthesizer, which generates the contents as an audio signal when a predetermined data is input, and is mainly a read-only memory ( It consists of integrated circuits such as ROM). The speech synthesizer is well known, and its details will be omitted. A code converter 14 converts the outputs of the counters 5 to 8 into codes suitable for the input of the speech synthesizer 13. Reference numeral 15 denotes a speaker, which generates the contents of the input data as audio in accordance with the audio signal from the audio synthesizer 13.
In addition, for the following explanation, the terminal 13a of the speech synthesizer 13
It is assumed that the logic value "0" (hereinafter, the logic values are simply referred to as "0" and "1") is generated while the audio signal is being generated, and the logic value "1" is generated while the audio signal is stopped.
Further, when the terminal 13b is held at "1", the input data is converted into an audio signal. 16 is a timing pulse generation circuit, 17 to 20 are delay type flip-flop circuits, and 21 is a detection circuit consisting of a counter, etc., which detects the period of the pulse generated from the pulse generation circuit 3 in three stages,
When time t ₁ < time t ₂ , pulse period t is t
When ≦t ₁ , to terminal a, and when t ₁ <t≦t ₂ , to terminal b,
When t ₂ <t, "1" is generated at terminal c. 2
2 to 25 are S-R flip-flop circuits, 26 to 25 are S-R flip-flop circuits;
28 is a differential circuit, 29 to 55 are gate circuits, 56
57 is an inverter, 57 is a switch, and 58 to 60 are gate circuits.

Next, the operation will be explained. When the switch 57 is closed, the gate circuit 38 is open, and the one-minute signal is supplied from the frequency divider 2 to the counter 5, thereby performing normal time measurement. If the switch 57 is opened in this state, timing can be adjusted. That is, gate circuit 38 is closed and gate circuit 36 is opened. On the other hand, by opening the above switch, the differential circuit 2
A pulse is generated at 8 to set flip-flop circuits 22-25 via gate circuit 31 and each gate circuit 45-48. Also gate circuit 3
The output pulse of 1 becomes the clock input of the flip-flop circuit 20 via gate circuits 37 and 32. Here, the gate circuit 33 produces an output of "1" because the output terminal Q of the flip-flop circuit 18 is "0" and the terminal 13a of the speech synthesizer 13 is "1". Therefore, when the above clock is input, the output terminal Q of the flip-flop circuit 20 becomes "1", and the input to the gate circuit 32 is prohibited. Furthermore, the output of the gate circuit 34 is also “1”
This becomes the clock input of the timing pulse generation circuit 16, and generates a pulse at the output terminal _Q4 .
On the other hand, since the flip-flop circuit 18 has a high frequency pulse _φ1 applied to its clock input,
After input D becomes “1”, output terminal Q becomes “1”
to be reversed. Since the flip-flop circuit 19 also receives the pulse φ ₁ as a clock input, after the output of the output terminal Q of the flip-flop circuit 18 is inverted to "1", the flip-flop circuit 19
The output terminal of is inverted to "0". Now, when the output terminal Q of the flip-flop circuit 18 becomes "1", the output of the gate circuit 33 becomes "0", so the output of the gate circuit 34 becomes "0", and when the pulse φ ₁ is applied, the flip-flop circuit 18
The output terminal Q of becomes "0". As a result, the output of the gate circuit 33 becomes "1" again, and therefore the output of the gate circuit 34 becomes "1", and at the same time as the pulse of the output terminal _Q4 of the timing pulse generation circuit 16 stops, the output of the output terminal Q3 becomes "_1" . A pulse is generated. On the other hand, the output of the output terminal Q of the flip-flop circuit 18 is again inverted to "1", and the output of the flip-flop circuit 18 is inverted to "1" again.
The output of the output terminal 9 is inverted to "0". By repeating this operation, the gate circuit 3
A pulse synchronized with pulse _φ1 is generated at the output terminal of timing pulse generation circuit 16.
Generate timing pulses sequentially on Q ₂ and Q ₁ .
When a pulse is generated from the output terminal _Q5 , the flip-flop circuit 20, the timing pulse generation circuit 16, and the flip-flop circuits 22 to 25
is reset. As described above, each time a pulse is applied to the clock input of the flip-flop circuit 20, the timing pulse generation circuit 16 generates one cycle of timing pulses.

Now, the switch 57 is opened, the flip-flop circuits 22 to 25 are set as described above, and the pulse generated at the output terminal _Q4 from the timing pulse generation circuit 16 causes the gate circuits 54 and 55 to be set.
When the output of the gate circuit 35 becomes "1" and the output terminals Q and of the flip-flop circuits 18 and 19 become "1", the output of the gate circuit 35 becomes "1".
become. Therefore, "1" is input to the terminal 13b of the speech synthesizer 13, and the input data being input to the speech synthesizer 13 is converted into an audio signal. The input data is the contents of counters 5-8 at the time the switch 57 was opened. That is, the pulse generated at the output terminal _Q4 of the timing pulse generating circuit 16 transfers the time measurement data from the counters 5-8 to the latch circuits 9-12. In addition, the above output terminal Q ₄
When a pulse occurs, morning or afternoon clock data is passed through gate circuits 43 and 44 and converted by code converter 14 into a code suitable for speech synthesizer 13. The converted clock data is converted into an audio signal by the audio synthesizer 13, and the content is announced as a voice from the speaker 15.

Next, the output terminal of the timing pulse generation circuit 16
When a pulse is generated at Q ₃ , the gate circuit 42 is opened and the clock data of the hour digit is sent to the gate circuits 42 and 44.
and a speech synthesizer 13 via a code converter 14
is input. The content is converted into an audio signal,
This is announced from the speaker 15. Below are the output terminals Q ₂ and Q ₁ of the timing pulse generation circuit 16.
As pulses are generated sequentially, gate circuits 41 and 40 are opened, two-digit and one-digit minute data are sequentially input to speech synthesizer 13, and the contents are announced from speaker 15.

Output terminal Q ₅ of timing pulse generation circuit 16
When a pulse is generated, flip-flop circuits 20, 22-25 and timing pulse generating circuit 16 are reset as described above. Therefore, the outputs of gate circuits 51 to 54 are held at "0". Furthermore, when the audio signal from the audio synthesizer 13 stops, the output of the terminal 13a becomes "1", so one input of the gate circuit 33 is also held at that value.

The operations during timing are as follows. When a pulse is generated from the pulse generation circuit 3, the gate circuit 3
6 and 39 to the counter 5, and its contents are changed. On the other hand, the output pulse of the gate circuit 36 is the differential circuit 27 and the gate circuits 37, 3.
2 becomes the clock input of the flip-flop circuit 20, and generates timing pulses at the output terminals _Q4 to _Q1 of the timing pulse generation circuit 16 by the same operation as described above. Also gate circuit 3
The above output pulse of 6 is applied to the flip-flop circuit 1.
7 and generates a pulse at its output terminal Q. As a result, the pulse φ ₂ is input to the detection circuit 21 via the gate circuit 30, one cycle of the pulse is timed, and an output is generated at one of the output terminals a, b, and c depending on the length of the pulse. Now, if a long-period pulse is generated from the pulse generation circuit 3 and an output is generated at the output terminal c, the output of the gate circuit 48 becomes "1", the flip-flop circuit 25 is set, and the output is generated at the output terminal Q. The output "1" causes the input of the gate circuit 51 to be held at that value. Here, the flip-flop circuits 22 to 24 are the timing pulse generating circuit 16.
The gate circuits 52 to 54 are closed because they are reset by the output of the output terminal _Q5 . As a result, when a pulse is generated at the output terminal _Q1 of the timing pulse generation circuit 16, the one-digit minute data stored in the latch circuit 9 is transmitted via the gate circuits 40, 44 and the code converter 14. The signal is input to the speech synthesizer 13. Further, since the output terminal 13b of the gate circuit 35 becomes "1", the content of the one-digit minute minute is announced from the speaker 15.

Assume that the period of the output pulse from the pulse generation circuit 3 is shorter than that described above, and an output is generated at the output terminal b of the detection circuit 21. In this case, since only the flip-flop circuit 24 is set, the gate circuit 52
One input of the gate circuit becomes "1", and the other gate circuits 51, 53 and 54 are closed. Therefore, when a pulse is generated at the output terminal Q ₂ of the timing pulse generation circuit 16, the two-digit minute clock data stored in the latch circuit 10 is input to the speech synthesizer 13, and its contents are broadcast from the speaker 15. be done.

When an output is generated at the output terminal a of the detection circuit 21, the content of the hour digit is changed to the speaker 1 in the same manner as above.
Notification will be made from 5.

Next, when a carry output occurs in any of the counters 5 to 7, the contents of the counter that received the output are notified, and this operation will be explained below. Suppose now that an output is generated at the output terminal b of the detection circuit 21, and that after the speaker 15 has uttered the two-digit time measurement contents of minutes, the counter 6 has outputted an extra digit. This carry output is the flip-flop circuit 59.
This output also sets the flip-flop circuit 23. Therefore, when a pulse is generated at the output terminal _Q3 during the generation of the timing pulse of the next cycle when the two digits of the minute are uttered, the contents of the hour digit of the counter 7 are notified. Note that the flip-flop circuit 59 is reset by the output of the gate circuit 53. The same applies to other carry cases.

When the pulses from the pulse generation circuit 3 are stopped for a certain period of time due to the end of time adjustment, etc., the following operation is performed. When the generation of pulses stops, the reset of the timer 4 is released, and the counting of the pulse φ ₃ supplied from the frequency divider 2 is continued. After a certain period of time, for example, 5 seconds, an output is generated from the timer 4, and the gate is activated. Flip-flop circuits 22-25 are set via circuits 31 and 45-48. Therefore, the gate circuits 51 to 54 are opened, and the operating state is the same as that when the switch 57 was opened, as described above, and the contents of the counters 5 to 8 are transmitted from the speaker 15.
Announcements are made in the order of morning or afternoon, hour, minute, two digits, and one digit.

According to the present invention, the counter of a desired stage is selected according to the period of the timing pulse supplied to the counter of the highest stage, and after this counter is incremented, the contents are announced by voice. , the timing digit can be selected according to the speed of the timing pulse, and only that digit is audibly announced, so you can check the timing content in a short time regardless of the surrounding brightness.
Quick and reliable timing can be achieved.

Further, when a carry signal is generated from the counter of the selected stage due to time adjustment, the carried contents are also announced by voice, so that the time adjustment time can be accurately notified.

In addition, after the timing pulse has stopped for a certain period of time, the contents of the counters at each stage are sequentially announced by voice, so the end of timing is automatically detected and the time after timing is read back. This allows you to reconfirm the timing details.

[Brief explanation of drawings]

The drawing is an electrical circuit diagram showing an embodiment of the present invention. 3...Pulse generation circuit, 4...Counter, 5~
8...Counter, 9-12...Latch circuit, 13
...Speech synthesis circuit, 15...Speaker, 16...
Timing pulse generation circuit.

Claims (1)

[Scope of Claims] 1. A multi-stage counter that measures time based on a time signal, a timing means for supplying a timing pulse to the least significant digit of the counter, and a counter according to the period of the timing pulse. a selection means for generating a selection output of a counter of any stage selected by the selection means; a detection means for detecting generation of a carry signal from a counter of the stage selected by the selection means; After the counter of the second stage is incremented in response to the arrival of the timing pulse, the contents of this counter are announced by voice, and when a carry signal is detected by the detection means, this carry signal is input. What is claimed is: 1. A timepiece equipped with a voice generating device, characterized in that it comprises a voice synthesizing means for audibly reporting the contents of a counter in a stage that has been generated. 2. A multi-stage counter that measures time based on a time signal, a timing means for supplying a timing pulse to the least significant digit of the counter, and a timing means for supplying a timing pulse to the least significant digit of the counter, and a timing means for supplying a timing pulse to the least significant digit of the counter, and a selection means for generating a counter selection output; a detection means for detecting generation of a carry signal from the counter of the stage selected by the selection means; After being incremented in response to the arrival of the timing pulse, the contents of this counter are audibly announced, and when a carry signal is detected by the detection means, the counter of the stage to which this carry signal is input is A voice synthesis means for audibly announcing the content; a timer circuit that receives the timing pulse as input and generates an output when the timing pulse stops for a certain period of time; A timepiece equipped with a sound generating device, characterized in that it comprises a control means for sequentially supplying the contents of the counter to the above-mentioned sound synthesis means to issue a sound notification.