JPS6236548B2 - - Google Patents

Info

Publication number
JPS6236548B2
JPS6236548B2 JP55106530A JP10653080A JPS6236548B2 JP S6236548 B2 JPS6236548 B2 JP S6236548B2 JP 55106530 A JP55106530 A JP 55106530A JP 10653080 A JP10653080 A JP 10653080A JP S6236548 B2 JPS6236548 B2 JP S6236548B2
Authority
JP
Japan
Prior art keywords
signal
sound generation
reference signal
division ratio
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55106530A
Other languages
Japanese (ja)
Other versions
JPS5730979A (en
Inventor
Shunichi Makuta
Hiroshi Myasaka
Katsuhiko Takebe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rhythm Watch Co Ltd
Original Assignee
Rhythm Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rhythm Watch Co Ltd filed Critical Rhythm Watch Co Ltd
Priority to JP10653080A priority Critical patent/JPS5730979A/en
Priority to US06/281,291 priority patent/US4481852A/en
Publication of JPS5730979A publication Critical patent/JPS5730979A/en
Publication of JPS6236548B2 publication Critical patent/JPS6236548B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G10MUSICAL INSTRUMENTS; ACOUSTICS
    • G10KSOUND-PRODUCING DEVICES; METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING, NOISE OR OTHER ACOUSTIC WAVES IN GENERAL; ACOUSTICS NOT OTHERWISE PROVIDED FOR
    • G10K15/00Acoustics not otherwise provided for
    • G10K15/02Synthesis of acoustic waves
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G13/00Producing acoustic time signals
    • G04G13/02Producing acoustic time signals at preselected times, e.g. alarm clocks
    • G04G13/021Details

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • General Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Electrophonic Musical Instruments (AREA)

Description

【発明の詳細な説明】 本発明は時計用発音回路、特に鳥あるいは虫な
どの擬声音を発音することのできる時計用発音回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound generation circuit for a watch, and particularly to a sound generation circuit for a watch that can generate onomatopoeic sounds such as birds or insects.

発音機構を有する時計が周知であり、特にアラ
ーム時計あるいは報時時計などとして用いられて
いるが、これらの従来装置においては、アラーム
音あるいは報時音は通常の場合ブザーあるは棒鈴
をハンマで叩く音などで行なわれていた。そして
近年の電子時計においてはこのような発音機構に
も電子回路が用いられ、チヤイムなどによつてア
ラーム音あるいは報時音を形成することが行なわ
れてきた。
Clocks with a sounding mechanism are well known, and are particularly used as alarm clocks or time-signal clocks. In these conventional devices, the alarm sound or time-signal sound is usually generated by a buzzer or a bell with a hammer. It was performed with the sound of tapping. In recent electronic watches, electronic circuits have also been used for such sound-producing mechanisms, and alarm sounds or time-signal sounds have been generated by chimes and the like.

しかしながら、これらの従来装置では使用者に
快感を与える発音作用が必ずしも得られないとい
う問題があつた。
However, these conventional devices have a problem in that they do not necessarily provide a sounding effect that gives a pleasant feeling to the user.

本発明の目的は、使用者に心地良い音、具体的
には鳥の声あるいは虫の鳴き声を発生でき、かつ
多種類のこれら鳥あるいは虫の擬声音を簡単に切
替選択して所望の擬声音によりアラームあるいは
報時を行なう時計用発音回路を提供することにあ
る。
An object of the present invention is to generate a sound that is pleasant to the user, specifically, a bird's voice or an insect's cry, and to easily switch and select from a variety of bird or insect onomatopoeias to create a desired onomatopoeic sound. An object of the present invention is to provide a sound generation circuit for a clock that makes an alarm or a time signal.

上記目的を達成するために、本発明は、予め設
定された時刻に報知動作開始信号を出力する報知
動作開始装置と、この報知動作開始装置の出力端
子に接続され、通常は発振停止信号出力端子及び
リセツト信号出力端子から発振停止信号及びリセ
ツト信号を出力し、前記報知動作開始信号の存在
を条件として前記発振停止信号及びリセツト信号
の出力を解除する制御回路と、この制御回路の発
振停止信号出力端子に接続され、前記発振停止信
号の存在で発音基準信号を出力せず、前記発振停
止信号の解除に応答して一定周波数の発音周期基
準信号を出力する発音周期基準信号発生器と、前
記制御回路のリセツト信号出力端子にリセツト信
号入力端子が接続され、前記発音周期基準信号発
生器の発音周期基準信号出力端子にクロツク入力
端子が接続され、前記リセツト信号の解除に応答
して前記発音周期基準信号をカウントし、そのカ
ウントする各段の出力ごとに正転端子、反転端子
の出力端子を有する分周比選択カウンタと、この
分周比選択カウンタの全段出力の正転端子及び反
転端子対に接続され、これら正転端子と反転端子
をそれぞれ選択して各分周比選択信号出力端子に
接続する分周比切替スイツチと、前記制御回路の
発振停止信号出力端子に接続され、前記発振停止
信号の存在で発音基準信号を出力せず、前記発振
停止信号の解除に応答して前記発音周基準信号よ
り周波数の高い発音基準信号を出力する発音基準
信号発生器と、前記制御回路のリセツト信号出力
端子にリセツト信号入力端子が接続され、分周比
切替スイツチの各段の分周比選択信号出力端子に
複数の分周比選択入力端子が対応づけて接続さ
れ、発音基準信号発生器の発音基準信号出力端子
にクロツク入力端子が接続され、前記リセツト信
号の解除に応答して前記発音基準信号を前記各分
周比選択入力端子の状態に応じて分周し、その分
周信号を出力するプログラム分周器と、このプロ
グラム分周器に接続され、前記分周信号に応じて
発音素子を駆動する発音器と、を有することを特
徴とする。
In order to achieve the above object, the present invention provides a notification operation start device that outputs a notification operation start signal at a preset time, and an oscillation stop signal output terminal connected to the output terminal of the notification operation start device. and a control circuit that outputs an oscillation stop signal and a reset signal from a reset signal output terminal and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal exists, and an oscillation stop signal output of this control circuit. a sound generation period reference signal generator connected to a terminal, which does not output a sound generation reference signal in the presence of the oscillation stop signal, and outputs a sound generation period reference signal of a constant frequency in response to cancellation of the oscillation stop signal; A reset signal input terminal is connected to a reset signal output terminal of the circuit, a clock input terminal is connected to a sound generation period reference signal output terminal of the sound generation period reference signal generator, and the sound generation period reference is reset in response to the release of the reset signal. A frequency division ratio selection counter that counts signals and has an output terminal of a normal rotation terminal and an inversion terminal for each output of each stage to be counted, and a pair of normal rotation terminal and inversion terminal of the output of all stages of this frequency division ratio selection counter. a frequency division ratio changeover switch that selects the normal rotation terminal and the inversion terminal and connects them to each frequency division ratio selection signal output terminal; a sound generation reference signal generator that does not output a sound generation reference signal in the presence of the signal and outputs a sound generation reference signal having a higher frequency than the sound generation frequency reference signal in response to cancellation of the oscillation stop signal; and a reset signal for the control circuit. A reset signal input terminal is connected to the output terminal, and a plurality of frequency division ratio selection input terminals are connected in correspondence to the frequency division ratio selection signal output terminals of each stage of the frequency division ratio selection switch, so that the sound generation reference signal generator generates sound. A clock input terminal is connected to the reference signal output terminal, and in response to release of the reset signal, the frequency of the sound generation reference signal is divided according to the state of each frequency division ratio selection input terminal, and the frequency-divided signal is output. The present invention is characterized in that it includes a program frequency divider and a sound generator connected to the program frequency divider and driving a sound generating element in accordance with the frequency-divided signal.

また、本発明は、予め設定された時刻に報知動
作開始信号を出力する報知動作開始装置と、この
報知動作開始装置の出力端子に接続され、通常は
発振停止信号出力端子及びリセツト信号出力端子
から発振停止信号及びリセツト信号を出力し、前
記報知動作開始信号の存在を条件として前記発振
停止信号及びリセツト信号の出力を解除する制御
回路と、この制御回路の発振停止信号出力端子に
接続され、前記発振停止信号の存在で発音基準信
号を出力せず、前記発振停止信号の解除に応答し
て発音基準信号を出力する発音基準信号発生器
と、この発音基準信号発生器の発音基準信号出力
端子に接続され、発音基準信号を分周して発音基
準信号より周波数の低い一定周波数の発音周期基
準信号を出力する分周器と、前記制御回路のリセ
ツト信号出力端子にリセツト信号入力端子が接続
され、前記分周器の発音周期基準信号出力端子に
クロツク入力端子が接続され、前記リセツト信号
の解除に応答して前記発音周期基準信号をカウン
トし、そのカウントする各段の出力ごとに出力端
子を有する分周比選択カウンタと、この分周比選
択カウンタの少なくとも2個の特定段出力端子に
接続され、これら出力端子を互いに入れ替えて2
個以上の分周比選択信号出力端子に接続する分周
比切替スイツチと、前記制御回路のリセツト信号
出力端子にリセツト信号入力端子が接続され、分
周比選択カウンタ及び分周比切替スイツチの分周
比選択信号出力端子に複数の分周比選択入力端子
が対応づけて接続され、発音基準信号発生器の発
音基準信号出力端子にクロツク入力端子が接続さ
れ、前記リセツト信号の解除に応答して前記発音
基準信号を前記各分周比選択入力端子の状態に応
じて分周し、その分周信号を出力するプログラム
分周器と、このプログラム分周器に接続され、前
記分周信号に応じて発音素子を駆動する発音器
と、を有することを特徴とする。
The present invention also provides a notification operation start device that outputs a notification operation start signal at a preset time, and an output terminal connected to the output terminal of the notification operation start device, and normally from an oscillation stop signal output terminal and a reset signal output terminal. a control circuit that outputs an oscillation stop signal and a reset signal, and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal is present; A sound generation reference signal generator that does not output a sound generation reference signal in the presence of an oscillation stop signal and outputs a sound generation reference signal in response to cancellation of the oscillation stop signal, and a sound generation reference signal output terminal of this sound generation reference signal generator. a frequency divider which divides the frequency of the sound generation reference signal and outputs a sound generation period reference signal having a constant frequency lower than that of the sound generation reference signal; and a reset signal input terminal is connected to the reset signal output terminal of the control circuit; A clock input terminal is connected to the output terminal of the sound generation cycle reference signal of the frequency divider, the clock input terminal is configured to count the sound generation cycle reference signal in response to release of the reset signal, and has an output terminal for each output of each counting stage. It is connected to a frequency division ratio selection counter and at least two specific stage output terminals of this frequency division ratio selection counter, and these output terminals are exchanged with each other.
A frequency division ratio selection switch is connected to one or more frequency division ratio selection signal output terminals, and a reset signal input terminal is connected to a reset signal output terminal of the control circuit. A plurality of frequency division ratio selection input terminals are connected in correspondence with the frequency ratio selection signal output terminal, a clock input terminal is connected to the sound generation reference signal output terminal of the sound generation reference signal generator, and in response to the release of the reset signal, a clock input terminal is connected to the sound generation reference signal output terminal of the sound generation reference signal generator. a program frequency divider that divides the frequency of the sound generation reference signal according to the state of each frequency division ratio selection input terminal and outputs the frequency-divided signal; and a sound generator that drives the sound generating element.

更に、本発明は予め設定された時刻に報知動作
開始信号を出力する報知動作開始装置と、この報
知動作開始装置の出力端子に接続され、通常は発
振停止信号出力端子及びリセツト信号出力端子か
ら発振停止信号及びリセツト信号を出力し、前記
報知動作開始信号の存在を条件として前記発振停
止信号及びリセツト信号の出力を解除する制御回
路と、この制御回路の発振停止信号出力端子に接
続され、前記発振停止信号の存在で発音基準信号
を出力せず、前記発振停止信号の解除に応答して
発音基準信号を出力する発音基準信号発生器と、
この発音基準信号発生器の発音基準信号出力端子
に接続され、発音基準信号を分周して発音基準信
号より周波数の低い一定周波数の発音周期基準信
号を出力する分周器と、前記制御回路のリセツト
信号出力端子にリセツト信号入力端子が接続さ
れ、前記分周器の発音周期基準信号出力端子にク
ロツク入力端子が接続され、前記リセツト信号の
解除に応答して前記発音周期基準信号をカウント
し、そのカウントする各段の出力ごとに出力端子
を有する分周比選択カウンタと、この分周比選択
カウンタの特定段出力端子に接続され、この出力
端子と接地端子とを互いに切替えて分周比選択信
号出力端子に接続する分周比切替スイツチと、前
記制御回路のリセツト信号出力端子にリセツト信
号入力端子が接続され、分周比選択カウンタ及び
分周比切替スイツチの分周比選択信号出力端子に
複数の分周比選択入力端子が対応づけて接続さ
れ、発音基準信号発生器の発音基準信号出力端子
にクロツク入力端子が接続され、前記リセツト信
号の解除に応答して前記発音基準信号を前記各分
周比選択入力端子の状態に応じて分周し、その分
周信号を出力するプログラム分周器と、このプロ
グラム分周器に接続され、前記分周信号に応じて
発音素子を駆動する発音器と、を有することを特
徴とする。
Further, the present invention includes a notification operation start device that outputs a notification operation start signal at a preset time, and an output terminal of the notification operation start device that is connected to the output terminal, and normally starts oscillation from an oscillation stop signal output terminal and a reset signal output terminal. a control circuit that outputs a stop signal and a reset signal and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal is present; a sounding reference signal generator that does not output a sounding reference signal in the presence of a stop signal and outputs a sounding reference signal in response to cancellation of the oscillation stop signal;
a frequency divider connected to the sound generation reference signal output terminal of the sound generation reference signal generator and configured to divide the sound generation reference signal and output a sound generation period reference signal having a constant frequency lower than the sound generation reference signal; A reset signal input terminal is connected to the reset signal output terminal, a clock input terminal is connected to the sound generation period reference signal output terminal of the frequency divider, and the sound generation period reference signal is counted in response to the cancellation of the reset signal; A frequency division ratio selection counter has an output terminal for each output of each stage to be counted, and a frequency division ratio selection counter is connected to a specific stage output terminal of this frequency division ratio selection counter, and this output terminal and a ground terminal are switched to each other to select a frequency division ratio. A frequency division ratio selection switch is connected to the signal output terminal, a reset signal input terminal is connected to the reset signal output terminal of the control circuit, and a division ratio selection signal output terminal of the frequency division ratio selection counter and the frequency division ratio selection switch is connected to the reset signal output terminal of the control circuit. A plurality of frequency division ratio selection input terminals are connected in correspondence, a clock input terminal is connected to a sound generation reference signal output terminal of the sound generation reference signal generator, and in response to the cancellation of the reset signal, the sound generation reference signal is outputted to each of the sound generation reference signals. A program frequency divider that divides the frequency according to the state of the frequency division ratio selection input terminal and outputs the divided signal; and a sound generator that is connected to the program frequency divider and drives the sound generation element according to the frequency division signal. It is characterized by having a container.

以下図面に基づいて本発明を説明する。 The present invention will be explained below based on the drawings.

第1図には鳥のさえずりの音のモデル特性が示
され、横軸の時間に対して縦軸に発音周波数がと
られている。第1図から明らかなように、鳥のさ
えずりの擬声音はほぼ一定の発音周期Taにて繰
り返す周期的な波形を示し、各発音周期Ta内で
は連続的に周波数が減少する変化特性を示す。
FIG. 1 shows the model characteristics of the sound of a bird's song, with the sound frequency plotted on the vertical axis versus time on the horizontal axis. As is clear from Figure 1, the onomatopoeic sound of a bird's song exhibits a periodic waveform that repeats at a nearly constant pronunciation period T a , and has a changing characteristic in which the frequency continuously decreases within each pronunciation period T a . show.

勿論、第1図の特性図は極めて基本的なモデル
を示すものであり、実際の鳥のさえずりあるいは
虫の鳴き声は更に複雑に発音周期自体も変化し、
また発音周期Ta内での変化特性も複雑な特性と
なることは明らかである。
Of course, the characteristic diagram in Figure 1 shows an extremely basic model, and actual bird chirps or insect calls are much more complex, and the pronunciation period itself changes.
Furthermore, it is clear that the change characteristics within the sound generation period T a are also complex characteristics.

従つて、本発明において、発音周期Taで繰り
返し変化する周波数の発音作用を行うともにこの
時の周波数変化特性を任意に選択可能とすれば、
所望の鳥あるいは虫の擬声音を得ることができ、
これを時計のアラーム音、報時音あるいは報時作
用時のバツクグラウンド音として用いることによ
り極めて使用者に快感を与える発音時計を得るこ
とができる。
Therefore, in the present invention, if the sounding effect is performed at a frequency that repeatedly changes with the sounding period T a , and the frequency change characteristics at this time can be arbitrarily selected,
You can obtain the onomatopoeic sound of a desired bird or insect,
By using this as an alarm sound, a time signal sound, or a background sound during a time signal operation, it is possible to obtain a sound-producing timepiece that gives the user an extremely pleasant feeling.

本発明は、前述した基本原理に基づいた時計用
発音回路を提供するものであり、第2図にはその
第1番目の発明が示されている。
The present invention provides a clock sounding circuit based on the above-mentioned basic principle, and FIG. 2 shows the first invention.

第2図において、発音基準信号発生器10は一
定周波数の発音基準信号を出力し、第1図のよう
なモデル発音特性を得るためには、その最も高い
周波数である8KHzより十分に高い周波数を有す
る発音基準信号を出力する発振器から形成するこ
とが必要である。
In FIG. 2, the pronunciation reference signal generator 10 outputs a pronunciation reference signal of a constant frequency, and in order to obtain the model pronunciation characteristics as shown in FIG. It is necessary to form it from an oscillator that outputs a sound reference signal having the following characteristics.

発音基準信号発生器10の出力はプログラム分
周器12に供給され所定のプログラムに従つて発
音基準信号が分周され、周波数の変化する発音信
号としてプログラム分周器12から出力される。
プログラム分周器12は実施例において分周比を
予め任意に設定可能なプログラマブル分周器から
形成されており、所定のプログラムに従つて複数
の異なる分周比が順次選択され、該分周比にてク
ロツク入力に供給される発音基準信号を分周出力
することができる。
The output of the sound generation reference signal generator 10 is supplied to a program frequency divider 12, which divides the frequency of the sound generation reference signal according to a predetermined program, and outputs the result from the program frequency divider 12 as a sound generation signal whose frequency changes.
In the embodiment, the program frequency divider 12 is formed of a programmable frequency divider whose frequency division ratio can be arbitrarily set in advance, and a plurality of different frequency division ratios are sequentially selected according to a predetermined program. The tone generation reference signal supplied to the clock input can be frequency-divided and output.

前記プログラム分周器12のプログラムされた
分周比を順次選択するために、分周器12の各D
入力には分周比選択カウンタ14のQ出力がそれ
ぞれ供給されており、このQ出力すなわち分周比
選択信号によつて第1図の発音周期Ta内で変化
する周波数に対応した分周比がプログラム分周器
12から選択的に読み出されることとなる。分周
比選択カウンタ14はクロツク入力に供給される
発音周期基準信号を順次計数し、この時Qあるい
は出力すなわちカウント出力を分周比選択信号
として前記プログラム分周器12へ供給し、この
カウント出力によつてプログラム分周器12の分
周比が順次選択される。実施例における分周比選
択カウンタ14は所定数のクロツク入力を計数す
ることによつて繰り返し計数作用を行なう。
In order to sequentially select the programmed division ratios of the programmed frequency divider 12, each D of the frequency divider 12 is selected.
The Q output of the frequency division ratio selection counter 14 is supplied to each input, and the frequency division ratio corresponding to the frequency changing within the sound generation period T a shown in FIG. 1 is determined by the Q output, that is, the frequency division ratio selection signal. is selectively read out from the program frequency divider 12. The frequency division ratio selection counter 14 sequentially counts the sound generation period reference signal supplied to the clock input, and at this time supplies Q or the output, that is, the count output, to the program frequency divider 12 as a frequency division ratio selection signal, and outputs the count output. The frequency division ratio of the program frequency divider 12 is sequentially selected by . The frequency division ratio selection counter 14 in the embodiment performs a repetitive counting operation by counting a predetermined number of clock inputs.

本発明において特徴的なことは、分周比選択カ
ウンタ14の分周比選択信号は、分周比切替スイ
ツチ13を介してプログラム分周器12に供給さ
れていることであり、分周比切替スイツチ13の
各スイツチはその固定接点がプログラム分周器1
2の各D入力に接続され、またその両切替接点は
その一方が分周比選択カウンタ14の各Q出力に
そして他方が出力に接続されている。従つて、
分周比切替スイツチ13のいずれかのスイツチを
選択的に切り替えることによつて、分周比選択カ
ウンタ14からはその組み合わせ出力が任意に変
更してプログラム分周器12へ供給されることと
なり、所望の分周比選択順を設定することが可能
となる。
A characteristic feature of the present invention is that the frequency division ratio selection signal of the frequency division ratio selection counter 14 is supplied to the program frequency divider 12 via the frequency division ratio changeover switch 13. Each of the switches 13 has its fixed contact connected to the program frequency divider 1.
One of the switching contacts is connected to each Q output of the frequency division ratio selection counter 14, and the other is connected to the output. Therefore,
By selectively switching one of the frequency division ratio selection switches 13, the combined output from the frequency division ratio selection counter 14 can be arbitrarily changed and supplied to the program frequency divider 12. It becomes possible to set a desired frequency division ratio selection order.

前記分周比選択カウンタ14のクロツク入力に
発音周期基準信号を供給するために発音周期基準
信号発生器16が設けられ、発音周期Taは発音
周期基準信号によつて決定される。
A tone generation period reference signal generator 16 is provided to supply a tone generation period reference signal to the clock input of the frequency division ratio selection counter 14, and the tone generation period T a is determined by the tone generation period reference signal.

前記したプログラム分周器12の分周出力は、
発音器18に供給され、分周出力に応じて発音器
18の発音素子が駆動される。実施例における発
音器18は増幅器20及び発音素子を形成するス
ピーカ22を含み、プログラム分周器12の分周
出力が増幅器20で増幅された後スピーカ22を
駆動し、発音周期Taで繰り返し変化する周波数
の発音作用を行なうことができる。
The frequency divided output of the program frequency divider 12 described above is
The signal is supplied to the sound generator 18, and the sound generating elements of the sound generator 18 are driven in accordance with the frequency-divided output. The sound generator 18 in the embodiment includes an amplifier 20 and a speaker 22 forming a sound generation element, and after the frequency-divided output of the program frequency divider 12 is amplified by the amplifier 20, the speaker 22 is driven, and changes repeatedly with a sound generation period T a . It is possible to perform a sound effect at a certain frequency.

図示の様にアラーム時計に組み込まれており、
時計機構部24の目安接点26からアラーム信号
を検出し、該アラーム信号によつて制御回路28
を動作し、前記各回路の制御が行なわれる。すな
わち、制御回路28からは通常の場合プログラム
分周器12及び分周比選択カウンタ14へリセツ
ト信号が供給されており、また両基準信号発生器
10,16には発生停止信号が供給されている。
そして時計機構部24の目安接点26がオン作動
した時に、制御回路28はリセツト信号及び発振
停止信号を解除し、回路動作を開始させることが
できる。
It is incorporated into the alarm clock as shown in the diagram.
An alarm signal is detected from the reference contact 26 of the clock mechanism section 24, and the control circuit 28 is activated by the alarm signal.
is operated to control each of the circuits. That is, the control circuit 28 normally supplies a reset signal to the program frequency divider 12 and the frequency division ratio selection counter 14, and also supplies a generation stop signal to both reference signal generators 10 and 16. .
When the reference contact 26 of the clock mechanism section 24 is turned on, the control circuit 28 can cancel the reset signal and the oscillation stop signal and start the circuit operation.

第1番目の発明は以上の構成からなり、以下に
その作用を説明する。
The first invention has the above configuration, and its operation will be explained below.

まず、分周比切替スイツチ13の各スイツチ
が、第2図で示されるように、分周比選択カウン
タ14の各Q出力側に切り替えられている状態と
考える。
First, assume that each switch of the frequency division ratio changeover switch 13 is switched to each Q output side of the frequency division ratio selection counter 14, as shown in FIG.

時計の指示時刻が目安設定時刻に到達すると、
目安接点26がオン作動し、制御回路28は各回
路を動作状態とし、この結果、発音基準信号発生
器10からは一定周波数の発音基準信号、実施例
においては1MHzの基準信号をプログラム分周器
12に出力する。同時に発音周期基準信号発生器
16からは低周波数の、実施例においては380Hz
の発音周期基準信号が分周比選択カウンタ14へ
供給され、分周比選択カウンタ14はこの発音周
期基準信号の計数作用を開始する。カウンタ14
はその初期状態において各Q出力は「0000000」
となつており、この時にプログラム分周器12は
8KHzの発音信号を発音器18へ出力する。そし
て、分周比選択カウンタ14は発音周期基準信号
を計数するたびにそのQ出力を「0000001」、
「0000010」……と変化させ、プログラム分周器1
2はこの分周比選択信号に応じて予めプログラム
された分周比を選択し、この分周比に基づいて発
音基準信号を分周出力する。実施例において、プ
ログラム分周器12は順次その分周比を所定プロ
グラムで大きくする選択作用を行ない、この結
果、発音周期Ta内で第1図に示されるモード特
性に対応する周波数変換作用を行なうことができ
る。
When the time indicated on the watch reaches the estimated time,
The reference contact 26 turns on, and the control circuit 28 puts each circuit into operation. As a result, the sound reference signal generator 10 outputs a sound reference signal of a constant frequency, in this embodiment, a reference signal of 1 MHz, to the programmed frequency divider. Output to 12. At the same time, the sound generation period reference signal generator 16 outputs a low frequency signal, 380Hz in this embodiment.
The sound generation period reference signal is supplied to the frequency division ratio selection counter 14, and the frequency division ratio selection counter 14 starts counting the sound generation period reference signal. counter 14
In its initial state, each Q output is "0000000"
At this time, the program frequency divider 12 is
A sound signal of 8KHz is output to the sound generator 18. Then, each time the frequency division ratio selection counter 14 counts the sound generation period reference signal, its Q output is "0000001",
Change it to "0000010"... and program frequency divider 1
2 selects a preprogrammed frequency division ratio in accordance with this frequency division ratio selection signal, and outputs the frequency-divided sounding reference signal based on this frequency division ratio. In the embodiment, the program frequency divider 12 sequentially performs a selection operation to increase its frequency division ratio according to a predetermined program, and as a result, a frequency conversion operation corresponding to the mode characteristic shown in FIG. 1 is performed within the sound generation period T a . can be done.

分周比選択カウンタ14が27個の発音周期基準
信号を計数すると、そのカウント出力すなわち分
周比選択信号は「1111111」となり、この時プロ
グラム分周器12はその分周比が発音基準信号を
ほぼ4KHzに分周する分周比を選択することとな
る。そして、分周比選択カウンタ14は次の発音
周期基準信号の入力によりカウントアツプして初
期状態にもどり、再び繰り返し計数作用を続行す
ることとなる。
When the frequency division ratio selection counter 14 counts 27 sound generation period reference signals, its count output, that is, the frequency division ratio selection signal, becomes "1111111", and at this time, the program frequency divider 12 determines that the frequency division ratio corresponds to the sound generation reference signal. A frequency division ratio that divides the frequency to approximately 4KHz will be selected. Then, the frequency division ratio selection counter 14 counts up in response to the input of the next sound generation cycle reference signal, returns to the initial state, and repeats the counting operation again.

以上のようにして、第1実施例によれば、ほぼ
300ミリ秒程度の発音周期Taで繰り返し第1図の
特性に対応した第3図のような周波数変化を行な
い、発音器18はこの周波数が連続的に変化する
発音信号に応じて発音作用を行ない、使用者は鳥
のさえずりあるいは虫の声の擬声音としてアラー
ム報知を受けることができ、極めて心地よいアラ
ーム音を聞くことができる。
As described above, according to the first embodiment, approximately
The frequency changes as shown in FIG. 3 corresponding to the characteristics shown in FIG. 1 are repeated at a sound generation period T a of about 300 milliseconds, and the sound generator 18 performs a sound generation operation in response to a sound signal whose frequency continuously changes. As a result, the user can receive an alarm notification as an onomatopoeic sound of a bird's song or an insect's voice, and can hear an extremely pleasant alarm sound.

そして、本発明においては、前記分周比切替ス
イツチ13の切替によつて分周比選択順を任意に
設定することができ、発音周期Ta内での周波数
変化を更に複雑な変化とすることが可能となり、
また使用者がスイツチ切替操作のみの簡単な操作
によつて異なる発音特性を任意に選択設定できる
という特徴を有する。
Further, in the present invention, the frequency division ratio selection order can be arbitrarily set by switching the frequency division ratio changeover switch 13, and the frequency change within the sound generation period T a can be made into a more complex change. becomes possible,
Another feature is that the user can arbitrarily select and set different pronunciation characteristics by simply switching a switch.

本発明における分周比選択信号の組み合わせ出
力の変更は、第2図において、例えば6ビツト目
(n−1)の切替スイツチを前記Q出力から出
力に切り替える例として示されている。この場
合、分周比選択カウンタ14の出力は
「0100000」から開始され、順次発音周期信号の計
数毎に「0100001」、「0100010」……と変化し、27
個の発音周期基準信号を計数すると、そのカウン
ト出力すなわち分周比選択信号は「1011111」と
なる。従つて、この切替時におけるプログラム分
周器12の出力波形は第4図のようになり、第3
図と比較して、各発音周期Ta内の周波数変化を
著しく複雑とし、実際の鳥のさえずりなどに近い
発音作用が得られるという利点を有する。
The change in the combination output of the frequency division ratio selection signal in the present invention is shown in FIG. 2 as an example in which the changeover switch of the 6th bit (n-1) is changed from the Q output to the output. In this case, the output of the frequency division ratio selection counter 14 starts from "0100000" and sequentially changes to "0100001", "0100010", etc. every time the sound generation period signal is counted.
When the number of sound generation period reference signals is counted, the count output, that is, the frequency division ratio selection signal becomes "1011111". Therefore, the output waveform of the program frequency divider 12 at this switching time is as shown in FIG.
Compared to the diagram, the frequency changes within each sound generation period T a are significantly more complex, and the advantage is that a sound effect similar to that of an actual bird's song can be obtained.

以上のように、第1番目の発明によれば、分周
比切替スイツチ13の切替スイツチを任意に使用
者が操作することによつて、複雑な周波数変化特
性を有する発音作用を選択することが可能とな
り、多機能の発音時計を提供し得るという利点が
ある。
As described above, according to the first invention, the user can arbitrarily operate the changeover switch of the frequency division ratio changeover switch 13 to select a sound effect having complicated frequency change characteristics. This has the advantage of providing a multifunctional pronunciation clock.

本実施例はアラーム時計に組込まれ、制御回路
28には目安信号が供給されているが、本発明を
報時時計に組込むことも可能であり、各正時に報
時信号を供給して所望の報時作用あるいは報時作
用時のバツクグラウンド音を前記擬声音で行なう
ことも好適である。また実施例では時計機構部2
4はアナログ時計として示されているが、デジタ
ル時計その他を用いることも勿論可能である。
Although the present embodiment is incorporated into an alarm clock and a reference signal is supplied to the control circuit 28, it is also possible to incorporate the present invention into a time signal, and a desired time signal is supplied at each hour on the hour. It is also preferable to use the onomatopoeic sound as the background sound for the time signal function or the time signal function. In addition, in the embodiment, the clock mechanism section 2
Although 4 is shown as an analog clock, it is of course possible to use a digital clock or the like.

第5図には第2番目の発明が示され、第2図と
同一部材には同一符号を付して説明を省略する。
A second invention is shown in FIG. 5, and the same members as in FIG. 2 are given the same reference numerals and their explanations will be omitted.

この発明においては、発音周期基準信号発生器
が発音基準信号を分周して発音周期基準信号を出
力する分周器30から形成されており、発音基準
信号発生器10の発音基準信号が供給される多段
分周器からなり、第1番目の発明のような独立し
た発振器を必要としないという利点を有する。
In this invention, the sound generation period reference signal generator is formed of a frequency divider 30 that divides the frequency of the sound generation reference signal and outputs the sound generation period reference signal, and the sound generation reference signal of the sound generation reference signal generator 10 is supplied. This invention consists of a multi-stage frequency divider, and has the advantage of not requiring an independent oscillator like the first invention.

分周比切替スイツチ13が分周比選択カウンタ
14の少なくとも2個の出力を互いに切り替える
スイツチを含み、第5図においては、第6及び7
ビツトが切替可能に接続されており、この連動ス
イツチの切替によつて所望の分周比選択順を設定
することができる。そして、第6図には第2番目
の発明の発音信号出力が示され、第4図の波形と
異なる複雑な波形となることが理解され、スイツ
チ13の切替によつて第6図に示す波形と第1ま
たは3図に示す一般的な波形との切替を行なうこ
とができる。
The frequency division ratio selection switch 13 includes a switch that mutually switches at least two outputs of the frequency division ratio selection counter 14, and in FIG.
The bits are switchably connected, and by switching this interlocking switch, a desired frequency division ratio selection order can be set. FIG. 6 shows the sound generation signal output of the second invention, and it is understood that it has a complicated waveform different from the waveform in FIG. 4, and by switching the switch 13, the waveform shown in FIG. It is possible to switch between the waveform and the general waveform shown in FIG. 1 or 3.

第7図には第3番目の発明が示され、第5図と
類似するので同一部材には同一符号を付して説明
を省略する。
A third invention is shown in FIG. 7, and since it is similar to FIG. 5, the same members are given the same reference numerals and their explanation will be omitted.

分周比切替スイツチ13はプログラム分周器1
2の少なくとも1個の入力を対応する分周比選択
カウンタ14の出力と接地端子とに切替えるスイ
ツチからなり、第7ビツトの分周比選択信号が切
替制御されている。この第7図によれば、プログ
ラム分周器12の第7ビツト入力は常に「0」と
することができ、第8図の波形図で示されるよう
に、その発音周期Taは半分に短縮され、第3図
と第8図に示した発音信号を選択的に切り替える
ことができる。第8図から明らかなように、本発
明では発音周期Taが短縮するとともにこの結
果、周波数変化幅も小さくなり、擬声音の音調を
著しく変化できる利点を有する。
The frequency division ratio switch 13 is the program frequency divider 1.
The frequency division ratio selection counter 14 is composed of a switch that switches at least one input of the frequency division ratio selection counter 14 between the corresponding output of the frequency division ratio selection counter 14 and a ground terminal, and the frequency division ratio selection signal of the seventh bit is switched. According to this FIG. 7, the seventh bit input of the program frequency divider 12 can always be set to "0", and as shown in the waveform diagram of FIG. 8, the sound generation period T a is halved. The sound generation signals shown in FIG. 3 and FIG. 8 can be selectively switched. As is clear from FIG. 8, the present invention has the advantage that the sound generation period T a is shortened, and as a result, the width of frequency change is also reduced, and the tone of the onomatopoeic sound can be changed significantly.

以上説明したように、本発明によれば、所定の
発音周期で繰り返し変化する周波数の発音作用を
行ない、更に分周比切替スイツチの切替操作によ
つてこの周波数変化を適宜に切替変更することが
できるため、所望の鳥あるいは虫等の擬声音が得
られ、これによつて使用者が快感を得られるアラ
ームあるいは報時を行なう時計用発音回路を提供
できる。
As explained above, according to the present invention, it is possible to perform a sounding operation with a frequency that repeatedly changes at a predetermined sounding cycle, and further to switch and change this frequency change as appropriate by switching the frequency division ratio switch. Therefore, it is possible to obtain a desired onomatopoeic sound of a bird, insect, etc., thereby providing a sound generation circuit for a watch that makes an alarm or time signal that gives the user a sense of pleasure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明で得られる擬声音のモデル特性
図、第2図は第1発明にかかる時計用発音回路を
示すブロツク回路図、第3,4図はそれぞれ第1
発明おける発音信号特性図、第5図は第2発明を
示すブロツク回路図、第6図は第2発明における
発音信号特性図、第7図は第3発明を示すブロツ
ク回路図、第8図は第3発明における発音信号特
性図である。 Ta……発音周期、10……発音基準信号発生
器、12……プログラム分周器、13……分周比
切替スイツチ、14……分周比選択カウンタ、1
6……発音周期基準信号発生器、18……発音
器。
FIG. 1 is a model characteristic diagram of the onomatopoeic sound obtained by the present invention, FIG. 2 is a block circuit diagram showing the sound generation circuit for a clock according to the first invention, and FIGS.
Figure 5 is a block circuit diagram showing the second invention, Figure 6 is a diagram showing the sound generation signal characteristics in the second invention, Figure 7 is a block circuit diagram showing the third invention. It is a sound generation signal characteristic diagram in the third invention. T a ... Sound generation period, 10 ... Sound generation reference signal generator, 12 ... Program frequency divider, 13 ... Frequency division ratio selection switch, 14 ... Frequency division ratio selection counter, 1
6... Sound generation period reference signal generator, 18... Sound generator.

Claims (1)

【特許請求の範囲】 1 予め設定された時刻に報知動作開始信号を出
力する報知動作開始装置と、 この報知動作開始装置の出力端子に接続され、
通常は発振停止信号出力端子及びリセツト信号出
力端子から発振停止信号及びリセツト信号を出力
し、前記報知動作開始信号の存在を条件として前
記発振停止信号及びリセツト信号の出力を解除す
る制御回路と、 この制御回路の発振停止信号出力端子に接続さ
れ、前記発振停止信号の存在で発音周期基準信号
を出力せず、前記発振停止信号の解除に応答して
一定周波数の発音周期基準信号を出力する発音周
期基準信号発生器と、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、前記発音周期基準信
号発生器の発音周期基準信号出力端子にクロツク
入力端子が接続され、前記リセツト信号の解除に
応答して前記発音周期基準信号をカウントし、そ
のカウントする各段の出力ごとに正転端子、反転
端子の出力端子を有する分周比選択カウンタと、 この分周比選択カウンタの全段出力の正転端子
及び反転端子対に接続され、これら正転端子と反
転端子をそれぞれ選択して各分周比選択信号出力
端子に接続する分周比切替スイツチと、 前記制御回路の発振停止信号出力端子に接続さ
れ、前記発振停止信号の存在で発音基準信号を出
力せず、前記発振停止信号の解除に応答して前記
発音周期基準信号より周波数の高い発音基準信号
を出力する発音基準信号発生器と、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、分周比切替スイツチ
の各段の分周比選択信号出力端子に複数の分周比
選択入力端子が対応づけて接続され、前記発音基
準信号発生器の発音基準信号出力端子にクロツク
入力端子が接続され、前記リセツト信号の解除に
応答して前記発音基準信号を前記各分周比選択入
力端子の状態に応じて分周し、その分周信号を出
力するプログラム分周器と、 このプログラム分周器に接続され、前記分周信
号に応じて発音素子を駆動する発音器と、 を有することを特徴とする時計用発音回路。 2 予め設定された時刻に報知動作開始信号を出
力する報知動作開始装置と、 この報知動作開始装置の出力端子に接続され、
通常は発振停止信号出力端子及びリセツト信号出
力端子から発振停止信号及びリセツト信号を出力
し、前記報知動作開始信号の存在を条件として前
記発振停止信号及びリセツト信号の出力を解除す
る制御回路と、 この制御回路の発振停止信号出力端子に接続さ
れ、前記発振停止信号の存在で発音基準信号を出
力せず、前記発振停止信号の解除に応答して発音
基準信号を出力する発音基準信号発生器と、 この発音基準信号発生器の発音基準信号出力端
子に接続され、発音基準信号を分周して発音基準
信号より周波数の低い一定周波数の発音周期基準
信号を出力する分周器と、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、前記分周器の発音周
期基準信号出力端子にクロツク入力端子が接続さ
れ、前記リセツト信号の解除に応答して前記発音
周期基準信号をカウントし、そのカウントする各
段の出力ごとに出力端子を有する分周比選択カウ
ンタと、 この分周比選択カウンタの少なくとも2個の特
定段出力端子に接続され、これら出力端子を互い
に入れ替えて2個以上の分周比選択信号出力端子
に接続する分周比切替スイツチと、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、分周比選択カウンタ
及び分周比切替スイツチの分周比選択信号出力端
子に複数の分周比選択入力端子が対応づけて接続
され、発音基準信号発生器の発音基準信号出力端
子にクロツク入力端子が接続され、前記リセツト
信号の解除に応答して前記発音基準信号を前記各
分周比選択入力端子の状態に応じて分周し、その
分周信号を出力するプログラム分周器と、 このプログラム分周器に接続され、前記分周信
号に応じて発音素子を駆動する発音器と、 を有することを特徴とする時計用発音回路。 3 予め設定された時刻に報知動作開始信号を出
力する報知動作開始装置と、 この報知動作開始装置の出力端子に接続され、
通常は発振停止信号出力端子及びリセツト信号出
力端子から発振停止信号及びリセツト信号を出力
し、前記報知動作開始信号の存在を条件として前
記発振停止信号及びリセツト信号の出力を解除す
る制御回路と、 この制御回路の発振停止信号出力端子に接続さ
れ、前記発振停止信号の存在で発音基準信号を出
力せず、前記発振停止信号の解除に応答して発音
基準信号を出力する発音基準信号発生器と、 この発音基準信号発生器の発音基準信号出力端
子に接続され、発音基準信号を分周して発音基準
信号より周波数の低い一定周波数の発音周期基準
信号を出力する分周器と、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、前記分周器の発音周
期基準信号出力端子にクロツク入力端子が接続さ
れ、前記リセツト信号の解除に応答して前記発音
周期基準信号をカウントし、そのカウントする各
段の出力ごとに出力端子を有する分周比選択カウ
ンタと、 この分周比選択カウンタの特定段出力端子に接
続され、この出力端子と接地端子とを互いに切替
えて分周比選択信号出力端子に接続する分周比切
替スイツチと、 前記制御回路のリセツト信号出力端子にリセツ
ト信号入力端子が接続され、分周比選択カウンタ
及び分周比切替スイツチの分周比選択信号出力端
子に複数の分周比選択入力端子が対応づけて接続
され、発音基準信号発生器の発音基準信号出力端
子にクロツク入力端子が接続され、前記リセツト
信号の解除に応答して前記発音基準信号を前記各
分周比選択入力端子の状態に応じて分周し、その
分周信号を出力するプログラム分周器と、 このプログラム分周器に接続され、前記分周信
号に応じて発音素子を駆動する発音器と、 を有することを特徴とする時計用発音回路。
[Scope of Claims] 1. A notification operation start device that outputs a notification operation start signal at a preset time; and a device connected to an output terminal of the notification operation start device,
A control circuit that normally outputs an oscillation stop signal and a reset signal from an oscillation stop signal output terminal and a reset signal output terminal, and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal exists; A sound generation period that is connected to the oscillation stop signal output terminal of the control circuit, does not output a sound generation cycle reference signal in the presence of the oscillation stop signal, and outputs a sound generation cycle reference signal of a constant frequency in response to cancellation of the oscillation stop signal. A reset signal input terminal is connected to a reference signal generator and a reset signal output terminal of the control circuit, a clock input terminal is connected to a sound generation cycle reference signal output terminal of the sound generation cycle reference signal generator, and the reset signal is released. a frequency division ratio selection counter that counts the sound generation period reference signal in response to the frequency division ratio selection counter and has an output terminal of a normal rotation terminal and an inversion terminal for each output of each counting stage, and outputs of all stages of the frequency division ratio selection counter. a frequency division ratio switching switch connected to a normal rotation terminal and an inversion terminal pair of the control circuit, and selecting the normal rotation terminal and the inversion terminal, respectively, and connecting them to each frequency division ratio selection signal output terminal; and an oscillation stop signal output of the control circuit. a sound generation reference signal generator connected to the terminal, which does not output a sound generation reference signal in the presence of the oscillation stop signal, and outputs a sound generation reference signal having a higher frequency than the sound generation cycle reference signal in response to release of the oscillation stop signal; A reset signal input terminal is connected to the reset signal output terminal of the control circuit, and a plurality of frequency division ratio selection input terminals are connected in correspondence to the frequency division ratio selection signal output terminals of each stage of the frequency division ratio selection switch. , a clock input terminal is connected to the sounding reference signal output terminal of the sounding reference signal generator, and in response to the release of the reset signal, the sounding reference signal is frequency-divided according to the state of each of the frequency division ratio selection input terminals. and a program frequency divider that outputs the frequency-divided signal; and a sound generator connected to the program frequency divider and that drives a sound element according to the frequency-divided signal. circuit. 2. A notification operation start device that outputs a notification operation start signal at a preset time; and a device connected to an output terminal of the notification operation start device;
A control circuit that normally outputs an oscillation stop signal and a reset signal from an oscillation stop signal output terminal and a reset signal output terminal, and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal exists; a sound generation reference signal generator that is connected to an oscillation stop signal output terminal of a control circuit, does not output a sound generation reference signal in the presence of the oscillation stop signal, and outputs a sound generation reference signal in response to cancellation of the oscillation stop signal; a frequency divider connected to the sound generation reference signal output terminal of the sound generation reference signal generator and configured to divide the sound generation reference signal and output a sound generation period reference signal having a constant frequency lower than the sound generation reference signal; A reset signal input terminal is connected to the reset signal output terminal, a clock input terminal is connected to the sound generation period reference signal output terminal of the frequency divider, and the sound generation period reference signal is counted in response to the cancellation of the reset signal; A frequency division ratio selection counter having an output terminal for each output of each stage to be counted; and a frequency division ratio selection counter connected to at least two specific stage output terminals of this frequency division ratio selection counter; A frequency division ratio selection switch is connected to the frequency division ratio selection signal output terminal, and a reset signal input terminal is connected to the reset signal output terminal of the control circuit, and the frequency division ratio selection counter and the frequency division ratio selection switch are connected to each other. A plurality of frequency division ratio selection input terminals are connected to the signal output terminal in correspondence with each other, a clock input terminal is connected to the sound generation reference signal output terminal of the sound generation reference signal generator, and the sound generation standard is set in response to the cancellation of the reset signal. a program frequency divider that divides the frequency of the signal according to the state of each frequency division ratio selection input terminal and outputs the frequency-divided signal; and a sound generating element connected to the program frequency divider according to the frequency division signal. A sound generation circuit for a watch, comprising: a sound generator for driving; and a sound generation circuit for a watch. 3. A notification operation start device that outputs a notification operation start signal at a preset time; and a device connected to an output terminal of the notification operation start device,
A control circuit that normally outputs an oscillation stop signal and a reset signal from an oscillation stop signal output terminal and a reset signal output terminal, and releases the output of the oscillation stop signal and reset signal on the condition that the notification operation start signal exists; a sound generation reference signal generator that is connected to an oscillation stop signal output terminal of a control circuit, does not output a sound generation reference signal in the presence of the oscillation stop signal, and outputs a sound generation reference signal in response to cancellation of the oscillation stop signal; a frequency divider connected to the sound generation reference signal output terminal of the sound generation reference signal generator and configured to divide the sound generation reference signal and output a sound generation period reference signal having a constant frequency lower than the sound generation reference signal; A reset signal input terminal is connected to the reset signal output terminal, a clock input terminal is connected to the sound generation period reference signal output terminal of the frequency divider, and the sound generation period reference signal is counted in response to the cancellation of the reset signal; A frequency division ratio selection counter having an output terminal for each output of each stage to be counted, and a frequency division ratio selection counter connected to a specific stage output terminal of this frequency division ratio selection counter, and switching this output terminal and a ground terminal to each other to select a frequency division ratio. A frequency division ratio selection switch is connected to the signal output terminal, a reset signal input terminal is connected to the reset signal output terminal of the control circuit, and a division ratio selection signal output terminal of the frequency division ratio selection counter and the frequency division ratio selection switch is connected. A plurality of frequency division ratio selection input terminals are connected in correspondence, a clock input terminal is connected to a sound generation reference signal output terminal of the sound generation reference signal generator, and in response to the cancellation of the reset signal, the sound generation reference signal is outputted to each of the sound generation reference signals. A program frequency divider that divides the frequency according to the state of the frequency division ratio selection input terminal and outputs the divided signal; and a sound generator that is connected to the program frequency divider and drives the sound generation element according to the frequency division signal. What is claimed is: 1. A sounding circuit for a watch, comprising:
JP10653080A 1980-07-10 1980-08-01 Sound generator for clock Granted JPS5730979A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10653080A JPS5730979A (en) 1980-08-01 1980-08-01 Sound generator for clock
US06/281,291 US4481852A (en) 1980-07-10 1981-07-07 Sound generating circuit for timepiece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10653080A JPS5730979A (en) 1980-08-01 1980-08-01 Sound generator for clock

Publications (2)

Publication Number Publication Date
JPS5730979A JPS5730979A (en) 1982-02-19
JPS6236548B2 true JPS6236548B2 (en) 1987-08-07

Family

ID=14435937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10653080A Granted JPS5730979A (en) 1980-07-10 1980-08-01 Sound generator for clock

Country Status (1)

Country Link
JP (1) JPS5730979A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245650U (en) * 1988-09-24 1990-03-29

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576484A (en) * 1984-07-05 1986-03-18 Grossmeyer Mark C Memory enhancing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245650U (en) * 1988-09-24 1990-03-29

Also Published As

Publication number Publication date
JPS5730979A (en) 1982-02-19

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