JPS6232426B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is capable of generating an electronic bell sound, that is, an electronic pseudo-bell sound similar to the bell sound of a motor-driven bell striking mechanism, and a case of generating an electronic sound using a normal audible frequency signal. It is possible to switch between the two cases.

BACKGROUND ART Alarm clocks and other devices have conventionally used a bell sound produced by a striking mechanism, an electronic sound, or a melody sound. Among these, the bell sound produced by the bell-striking mechanism has been preferred since it has a great alarming effect. In order to generate this bell sound, conventionally the bell striking mechanism was driven by a DC motor, which generated the desired bell sound, but the structure of the bell striking mechanism using a DC motor was complicated. In addition, the bell-striking mechanism made the clock larger, and the DC motor drive increased current consumption, among other drawbacks.

In recent years, in order to overcome these drawbacks, mechanisms have been developed to electronically generate bell sounds without using the conventional bell striking mechanism, and as a result, each different audio frequency signal is periodically attenuated and modulated. It was discovered that by creating a signal that was similar to that of a bell, and superimposing these signals to create a sound, a sound very similar to a bell sound could be generated. Then, as a method of periodically attenuating and modulating the audio frequency signal, multiple
A configuration has been proposed in which a gate circuit supplied with an audio frequency signal is connected to each gate input of a group of MOS transistors, and a signal is supplied to each gate circuit to periodically and sequentially turn off each MOS transistor. This makes it easier to incorporate the method into an integrated circuit, making it easier to commercialize the pseudo-bell sound generation method.

However, in recent years, the range of users of alarm clocks has become wider, and users' demands for alarm sounds have also become more diverse, and it has become impossible to meet all of users' demands simply by providing a bell sound that has a large alarm effect. Therefore, in recent years, in addition to bell sounds, electronic sounds,
The user can select a melody sound, etc., or a melody sound or an electronic sound every certain period of time.
A system that changes to a bell sound has been proposed and is being implemented. However, these conventional methods require separate mechanisms to generate the bell sound and electronic or melody sounds.
This led to higher costs and larger watches. In particular, if the method of generating the bell sound is to drive the bell striking mechanism with a DC motor, the bell sound generating mechanism is completely separate from the mechanism that generates electronic sounds or melody sounds, and there are no common parts, so the clock Miniaturization,
This has been a major obstacle to cost reduction, and improvements have been desired.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to generate an electronic sound or melody sound without separately providing a mechanism for generating an electronic sound or a melody sound and a mechanism for generating a bell sound. To provide an alarm sound generation circuit for a clock capable of generating a sound and a bell sound.

In order to achieve the above object, the present invention provides a plurality of devices connected in parallel to generate a pseudo bell sound.
at least two attenuation modulation circuits each having a group of MOS transistors and a gate circuit connected to the gate input of each MOS transistor; an attenuation control circuit for providing an attenuation control signal, and periodically attenuating the different audio frequency signals from each attenuation control circuit by providing a different audio frequency signal to the gate circuit of each attenuation control circuit. When a pseudo bell sound is generated by superimposing sound, and when all other attenuation modulation circuits are disabled except for one attenuation modulation circuit, and one
Synthesis of specific MOS transistors in one attenuation modulation circuit by fixing the operating state of the attenuation control circuit so as to continue supplying an attenuation control signal that turns off only the specific MOS transistor in one attenuation modulation circuit The present invention is characterized in that it is configured to be switchable between generating sound using one type of audible frequency signal via an on-resistance.

Embodiments of the present invention will be described below based on the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. In FIG. 1, the circuit of the present invention is incorporated into an electronic alarm clock. The motor 18 includes a waveform shaping circuit 14 that shapes the waveform, a drive circuit 16 including an amplifier, and a clock synchronous motor 18.
The driving force is transmitted to the wheel train 20 to which the time indicator hand is fixed. The clock device also includes an alarm on/off switch 2 for operating the alarm mechanism.
2 and an alarm switch 24, the alarm on/off switch 22 is manually controlled on and off by the user to enable or disable the alarm mechanism, and the alarm switch 24 works in conjunction with the clock train 20 to set a desired alarm. It can be turned on at a set time to trigger an alarm. That is, when both the switches 22 and 24 are turned on at the alarm setting time, the reset state of the waveform shaping flip-flop (FF) 26 is released and the alarm trigger is activated in synchronization with the synchronization signal from the frequency dividing circuit 12. Signal K is output from the Q output terminal of FF26.

The present invention is characterized by at least two
There are two cases in which a pseudo-bell sound is generated by periodically attenuating and modulating audio frequency signals of different types and superimposing both of the attenuated and modulated output signals, and a case in which a pseudo-bell sound is generated by using these pseudo-bell sound generation circuits. For this purpose, the notification sound generation circuit includes a first attenuation modulation circuit 30, a second attenuation modulation circuit 40, and both attenuation modulation circuits 30, 40. an attenuation control circuit 50 and an attenuation modulation circuit 4 that supply an attenuation control signal with a predetermined period to
0 and a specific
It includes a switching gate circuit 60 that can be fixed in the operating state of the attenuation control circuit 50 so as to continue supplying an attenuation control signal that turns off only the MOS transistor,
Furthermore, it includes a sound generation circuit 80 which superimposes the output signals of both attenuation modulation circuits 30 and 40 to generate sound.

The first attenuation modulation circuit 30 consists of a resistance adjustment circuit, and includes eight MOS transistors 3 connected in parallel.
2, MOS transistor 3 in the embodiment
2 consists of a P channel open drain connection, and the current value of the output signal R changes depending on the combination of the on-operation resistances.

A NAND gate 34 is connected to the gate input of each MOS transistor 32, and a switching gate circuit 60 is connected to the input of each NAND gate 34.
, a first audio frequency signal C to be modulated from the frequency divider circuit 12, and an attenuation control signal L from the attenuation control signal circuit 50, respectively. In the example, the first audio frequency signal C is set at a frequency of 4KHz.

an attenuation control circuit 5 that outputs the attenuation control signal L;
0 consists of a step signal generator in which eight stages of FF52 are connected in series, the first stage FF52-1 is supplied with the alarm trigger signal K, the next stage and subsequent stages are supplied with the Q output of the previous stage, and the final stage FF52-8 is supplied with the Q output of the previous stage. Q output
_L8 is input to the reset input R of all FFs 52 via the OR gate 62 in the switching gate circuit 60. The pulse signal A of the frequency dividing circuit 12 is supplied to the clock input O/ of each FF 52, and the period of the attenuation control signal L is determined by the period of this pulse signal A. ,
Pulse signal A is set to 128 Hz, and as a result, one cycle of attenuation control signal L is set to 16 Hz.

The attenuation control circuit 50 further includes an inverter 54, and the Q output of each FF 52 is inverted by the inverter 54 and supplied as an attenuation control signal L to the input of the NAND gate 34 of the attenuation modulation circuit 30.

The second attenuation modulation circuit 40 also has a similar configuration to the first attenuation modulation circuit 30, and includes eight stages of MOS transistors 42 and a NAND gate 44.
A switching gate circuit 6 is connected to the input of the NAND gate 44.
0 output signal O of AND gate 64 and frequency divider circuit 1
A second audio frequency signal B from 2 and the attenuation control signal L are provided. In an example,
The frequency of the second audio frequency signal B is set to 2KHz.

The output signals R and S of both attenuation modulation circuits 30 and 40 are supplied to a sound generation circuit 80, which includes a piezoelectric element 82, a boosting coil 84, a drive transistor 86, and a wired OR gate 8.
8, the output signals of the two attenuation modulation circuits 30 and 40 are superimposed and supplied to the gate of the transistor 86, and the piezoelectric element 82 is driven and controlled by the superposition of the signals obtained by attenuation modulating the two audio frequency signals B and C. That will happen.

On the other hand, the switching gate circuit 60 includes an OR gate 6
2, 66, AND gates 64, 68, 70, an inverter 72, and a changeover switch 74. The output signal F of the changeover switch 74 is passed through an AND gate 68,
Input to inverter 72 and OR gate 62. Intermittent control signals D and E from the frequency dividing circuit 12 are also input to the AND gate 68, and in this embodiment, the signal D is set to 8 Hz and the signal E is set to 1 Hz. Output signal G of AND gate 68
is input to the OR gate 66 together with the output signal H of the inverter 72, and the output signal I of the OR gate 66 is input to the AND gate 70. and gate 70
The output signal N is input to one of the AND gates 64 and the NAND gate group 34 of the attenuation modulation circuit 30. Further, the output signal H of the inverter 72 is input to the other side of the AND gate 64, and the AND gate 64
The output signal O is input to the NAND gate group 44 of the attenuation modulation circuit 40.

On the other hand, the OR gate 62 also includes a damping control circuit 50.
The Q output signal 8 of the FF 52-8 is input, and the output signal M is supplied to each reset input R of the FF 52.

The embodiment of the present invention has the above configuration, and its operation will be explained below with reference to the waveform diagrams of FIGS. 2 and 3.

FIG. 2 is a waveform diagram when the changeover switch 74 is closed. Since the output signal F of the changeover switch 74 becomes L, the AND gate 68 is closed, and the signal of the OR gate 62 also becomes L, so that the reset of the FF group 52 is released. and inverter 72
Since the output signal H of is inverted and becomes H, the output signal I of the OR gate 66 becomes H.

When the alarm time arrives and the signal J becomes L, the reset of the FF 26 is released and the alarm trigger signal K, which is its Q output, is synchronized with the signal E.
It will be 2H. As a result, the output signal N of the AND gate 70 and the output signal O of the AND gate 64 both become H, and the signals N and O are supplied to the NAND gate groups 34 and 44, respectively. At the same time, the alarm trigger signal K, which became H,
It is input to the D input of the FF 52-1, and thereafter, in synchronization with the pulse signal A, the attenuation control signals L ₁ to L 8 are periodically changed to L in the order of _{L 8} . Due to this change in the attenuation control signal L, the attenuation modulation circuit 30 adjusts the resistance of the first audio frequency signal C by each MOS transistor 32. That is, in the initial stage when the signal N becomes H as the alarm trigger signal K becomes H, all the attenuation control signals L are applied to the NAND gate 3.
4 is opened, and as a result, the combined resistance of the attenuation modulation circuit 30 becomes the lowest, and as a result, the output R of the attenuation modulation circuit 30 has a large current value. From this initial state, the attenuation control circuit 50 sequentially cuts off its output signals L ₁ to L ₇ each time the pulse signal A is input, and accordingly, each MOS in the attenuation modulation circuit 30
Since the transistor 32 is turned off by the output signal F of the corresponding NAND gate 34, the combined resistance of the attenuation modulation circuit 30 increases sequentially, and accordingly,
The current value of the output signal R also decreases in stages.

Similar to the first attenuation modulation circuit 30 described above, the second attenuation modulation circuit 30
The attenuation modulation circuit 40 also modulates the second audio frequency signal B by the attenuation control signal L, and the NAND gate 4
The combined resistance of the MOS transistor 42 changes sequentially according to the output Q of the transistor 4, and by combining these, the output signal S can be obtained.

As is clear from FIG. 2, both attenuation modulation circuits 3
The output signals R and S of 0 and 40 have a characteristic of attenuating sequentially in multiple steps in a period T = 0.0625 seconds,
Since this is superimposed and supplied to the sound generation circuit 80,
The sound generation circuit 80 can generate a pseudo-bell sound that is very similar to the bell sound produced by a conventional bell-striking mechanism.

FIG. 3 is a waveform diagram when the changeover switch 74 is opened. In this case, the output signal F of the selector switch 74 becomes H, so the AND gate 68 opens.
The output signal of inverter 72 becomes L. Therefore, the output signal G of the AND gate 68 is an intermittent sound signal that becomes H only when both the intermittent sound control signals D and E are H, and the output signal I of the OR gate 66 also has a signal in phase with this signal. can get. Furthermore, since the output signal H of the inverter 72 is L, the AND gate 64 is closed.

Further, the output signal F of the changeover switch 74 causes the output signal M of the OR gate 62 to become H, thereby bringing the FF group 52 into a reset state.

When the alarm setting time arrives, the alarm trigger signal K becomes H as described above, thereby opening the AND gate 70. As a result, an intermittent tone signal in phase with the signal G is obtained as the signal N of the AND gate 70.
is closed in this state, so the attenuation modulation circuit 3
It is supplied only to the NAND gate 34 in 0 and not to the NAND gate 44 in the attenuation modulation circuit 40.

At the same time, the alarm trigger signal K is set to FF52.
-1, but at this time, the FF group 52
have been reset, so even if the pulse signal A is supplied, the attenuation control signals _L1 to _L7 maintain the H state. Therefore, all NAND gates 34 of the attenuation modulation circuit 30 are in an open state, so that the output R of the attenuation modulation circuit 30 has a large current value. On the other hand, the NAND gate 44 in the attenuation modulation circuit 40
are all closed, and nothing appears at the output S of the attenuation modulation circuit 40.

As a result, as shown in FIG. 3, only the output signal R of the attenuation modulation circuit 30 is supplied to the sound generation circuit 80, so that the sound generation circuit 80 generates a normal intermittent electronic sound.

In this way, according to this embodiment, the changeover switch 7
4, it is possible to generate a bell sound or a normal electronic sound, and the normal electronic sound utilizes the first attenuation modulation circuit 30 used to generate the bell sound. Therefore, there is no need to newly provide a circuit separate from the circuit for generating the bell sound. Furthermore, since the circuit configuration of the embodiment described above can be easily integrated into an integrated circuit, it is possible to reduce the size and cost, and the current consumption is much lower than that of a bell sound generating mechanism using a DC motor.

In this embodiment, a switch 74 operated externally by the user is used as a means for switching between a bell sound and a normal electronic sound, but there is also a switch 74 that detects that a certain period of time has elapsed since the alarm sound was generated. It is also possible to configure the system to automatically switch from an electronic sound to a bell sound, or from a bell sound to an electronic sound.

Furthermore, in this embodiment, the electronic sound is normally an intermittent sound made up of a 1Hz signal E and an 8Hz signal D.
By changing the signal taken out from the frequency dividing circuit 12 and the configurations of the AND gate 68 and the OR gate 66, different intermittent or continuous sounds can be produced.
Furthermore, when only the attenuation modulation circuit 30 is enabled, if a tone frequency signal for melody sound is supplied to the attenuation modulation circuit 30 instead of the audible frequency sound signal C, it is possible to switch between the bell sound and the melody sound. Become.

Furthermore, in this embodiment, when switching to normal electronic sound, the attenuation control circuit 50 is changed to the attenuation modulation circuit 30.
The operating state is fixed so as to continue supplying an attenuation control signal that turns on only a specific MOS transistor in the MOS transistor, and the second attenuation modulation circuit 40 is disabled. If you do this, you will be able to switch between the bell sound and the decaying sound.

As described above, according to the present invention, at least two
In some cases, a pseudo bell sound is generated by superimposing the output signals of both attenuation modulation circuits, and in other cases, a normal electronic sound is generated by turning on only a specific transistor in one attenuation modulation circuit. By configuring the bell sound and the electronic sound to be switchable, it is possible to switch between the bell sound and the electronic sound without providing separate and independent circuits. In addition, since attenuation modulation circuits and the like can be easily integrated into integrated circuits, watches can be made smaller and less expensive, and the current consumption is also lower than that of conventional bell sound generating mechanisms that use DC motors. There is.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
1 is a waveform diagram when a pseudo bell sound is generated in the circuit of FIG. 1, and FIG. 3 is a waveform diagram when a normal electronic sound is generated in the circuit of FIG. 1. 30...first attenuation modulation circuit, 32...MOS
Transistor, 34...Gate circuit, 40...Second attenuation modulation circuit, 42...MOS transistor, 44...Gate circuit, 50...Attenuation control circuit, 60...Switching gate circuit, 80...Sound generation circuit.

Claims (1)

[Claims] 1. A reference signal generator, a frequency dividing circuit that divides the frequency of the reference signal from the reference signal generator, a time display mechanism that displays the time using an output signal from the frequency dividing circuit, and An alarm switch that turns on when it detects that the time displayed on the time display mechanism has reached the set time, and an alarm trigger circuit that outputs an alarm trigger signal in response to the turn-on signal of this alarm switch. an attenuation control circuit that increases the number of output lines of the flip-flops that sequentially generate attenuation control signals in response to constant periodic signals from the frequency divider circuit from the time when the alarm trigger signal is generated; It consists of a plurality of MOS transistor groups connected in parallel and a gate circuit connected to the gate input of each MOS transistor, and each output line of the attenuation control circuit and the output line from the alarm trigger circuit are connected to this gate circuit. A first
and a second attenuation modulation circuit, which generates an output signal having a sounding intensity responsive to the composite on-resistance of the MOS transistors that increases sequentially when the alarm trigger signal is generated and in response to changes in the attenuation control signal. A timepiece further comprising: a sound generation circuit that superimposes output signals from the first and second attenuation modulation circuits to generate sound, an externally operable changeover switch; outputting a reset signal to the attenuation control circuit to stop generation of the attenuation control signal when the operation signal is generated;
1. An electronic alarm sound generation circuit for a watch, comprising: a switching gate circuit for blocking either one of the alarm trigger signals supplied to the attenuation modulation circuit.