JPS6215829B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm control circuit for a composite electronic timepiece with an alarm function, in which the time display means is composed of an analog display section using a hand and an electro-optical means.

In a composite electronic watch with an alarm function, the internal resistance of the small battery used as a power source increases at low temperatures. If an alarm is sounded at this time, the voltage of the battery will drop due to the large current flowing to the alarm circuit. Furthermore, if you attempt to drive the motor as the drive source for the analog display section at the same time as the alarm, the motor may not operate due to the low voltage. Therefore,
Generally, alarm control circuits are designed so that motor drive and alarm drive are not performed at the same time.
However, in conventional electronic watches with alarms, when the alarm consists of a number of continuous sounds such as chime sounds or melody sounds, making up one block and expressing various expressions, the continuous If there is a break in the width of the sound, the user will feel uncomfortable when listening to it, and the product will be incomplete. Also, if you try to synchronize the alarm sound with the motor drive, if there is a discrepancy between the second hand movements of the digital clock and analog clock, the alarm will sound unless you wait up to 1 second after the digital clock's alarm time matches. I can't start.
This is a major disadvantage in terms of use and image of a highly accurate watch.

The present invention eliminates such drawbacks, and its purpose is to set the alarm time of the digital clock without affecting the motor drive of the analog clock even when the seconds of the analog clock and digital clock are not completely synchronized. An object of the present invention is to provide an alarm control circuit for a composite electronic clock with an alarm, in which the alarm starts sounding with almost no delay when the matches match.

The present invention will be described in detail below based on Examples. FIG. 1 is a block diagram of a composite electronic timepiece with an alarm according to the present invention. 1 is an oscillation circuit that outputs a reference signal, 2 is a frequency dividing circuit that divides the frequency of the reference signal, 3 is an analog partial frequency circuit, 4 is a motor drive circuit, 5 is a motor, 6 is a digital partial frequency circuit,
7 is a digital decoder, 8 is a display driver,
9 is a display section, 10 is an alarm control circuit, 11 is an alarm driver, and 12 is a speaker. The clock is divided into a digital section and an analog section after a certain frequency division stage, and constitutes a separate clock. When the digital alarm times match in the 10 alarm control circuits that output acoustic signals to control sound generating devices such as the speakers 12, a chime sound signal is generated, and the 12 speakers emit a chime signal as shown in Figure 2. A chime sound with one block per second is generated. The vertical axis represents the sound pressure, and the horizontal axis represents the passage of time. The section of _t1 outputs 4096Hz in 0.25 seconds. The section of _t2 outputs 3276.8Hz in 0.75 seconds. _t3 is 0.0625
seconds, t ₄ is 0.5 seconds, t ₅ is 0.125 seconds, t ₆ and t ₇ are respectively
It is 0.0625 seconds. If you pay attention to this chime sound, 1
It can be seen that even if a pause period corresponding to the drive pulse of a motor is provided at positions 3, 14, 15, and 16, there is almost no effect on the auditory sense. This was also confirmed through experiments. Therefore, the circuit of this watch is designed to provide a pause section at the position of this chime sound and drive the motor. FIG. 3 shows the motor drive timing, digital alarm coincidence timing, and alarm start timing. here 35
indicates the motor drive pulse. Now, in the interval _t8 , when the alarm time of the digital clock matches and an alarm match signal is output, the alarm starts from position 17. That is, a chime sound having the pattern shown in FIG. 2 is emitted from position 17 in FIG. 3. Then, motor drive pulse 35
Since the timing position 16 in FIG. 2 overlaps with the position 16, the motor drive enters the position 16.
Similarly, when the alarm matches in the interval _t9 , the alarm starts at 18, and the motor starts driving at position 15. If the alarm matches in the section _t10 , the alarm starts at 19 and the motor starts driving at position 14. When the alarm matches in the section of t ₁₁ , the alarm starts at 20 and 1
The motor is activated at position 3. Therefore,
The alarm starts sounding with a maximum delay of 0.5 seconds after the alarm matches. FIG. 4 is a specific circuit diagram of an alarm control circuit that outputs an alarm start signal from a frequency-divided signal of an analog section and a frequency-divided signal of a digital section. 21, 22, 23, and 24 are 1/2 frequency divider circuits whose output data changes at the falling edge of the clock;
5, 26 are AND circuits, 27 is OR circuit, 28 is
NOT circuit, 29 is a 1/2 frequency divider circuit with data input,
30 is a NOT circuit, 31, 32, 33 are NAND circuits, and 34 is an AND circuit. S ₁ is an 8Hz signal from the analog section, S ₂ is the same 4Hz signal, and S ₃ is the same 2Hz signal.
The signal _S4 is also a 1Hz signal. S ₅ is alarm start trigger signal, S′ ₅ is 1/2 with data input
The output signal of the frequency dividing circuit 29, S ₆ is 1 of the digital section.
Differential signal at Hz carry, S ₇ is analog section 16
Hz signal, _S8 is the analog section reset signal, _S9 is the alarm match signal, _S10 is the alarm ringing command signal, _S11
is an alarm start signal. FIG. 5 is a timing chart of the circuit of FIG. 4. This timing chart shows the case where the alarm starts sounding 0.125 seconds after the alarm matches. Motor drive is performed in synchronization with the falling edge of _S4 .
When the _S9 signal rises to indicate a digital alarm match, the _S6 differential signal is simultaneously output and resets the 29 1/2 frequency divider circuit. At this time, S′ ₅ which is the output of the 1/2 frequency divider circuit with data input
is a logic level H (hereinafter abbreviated as H; similarly, logic level L is indicated as L). Next, when the output of _S5 becomes H, the output of _S'5 remains H, so the output of _S11 becomes L. When the output of _S5 becomes L, the output _S'5 also latches VDD as data and becomes L, so the output of _S11 becomes H. In other words, the output of _S10 becomes H in synchronization with the first rise of the output of _S11 after the alarm coincidence signal is output from the digital section, and the alarm starts. _S10 and _S11 are input to the alarm generation circuit, the signal of _S11 becomes the initial setting trigger signal of the alarm generation circuit, and _S10 becomes the signal indicating the output state of the alarm. The alarm generating circuit outputs a signal as shown in FIG. In the case of Fig. 5, the alarm starts 0.125 seconds after the alarm matches, and the motor is driven at position 13 in Fig. 2. Therefore, the alarm generation circuit outputs an alarm signal in which the alarm output of the portion 13 in FIG. 2 is suspended. This alarm generation circuit can be configured with a 1/2 frequency divider circuit, an AND circuit, an OR circuit, a NOT circuit, and the like. Further, the circuit shown in FIG. 4 is an example of the present invention, and the present invention can be implemented with other circuit configurations. In addition to chime sounds, it can be widely applied to melodies, etc.

As described above, according to the present invention, even when the digital part and the analog part do not match, the alarm starts sounding with almost no time delay after the alarm matches. Moreover, since the alarm pause period for driving the motor is placed in the part that has the least effect on the chime sound and other tones, the chime sound and other tones are seamless and smooth, providing excellent effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a composite electronic clock with an alarm according to the present invention, Fig. 2 is an example of an alarm sound according to the present invention, and Fig. 3 is a diagram showing motor drive timing, digital alarm matching timing, and alarm ringing according to the present invention. 4 is a diagram showing the initial timing, FIG. 4 is a specific example of the alarm control circuit according to the present invention, and FIG. 5 is a timing chart of FIG. 4. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Frequency division circuit, 3... Analog partial frequency circuit, 4... Motor drive circuit, 5... Motor, 6... Digital partial frequency circuit, 7... Digital decoder, 8... Display driver, 9... Display section, 10
...Alarm control circuit, 11...Alarm driver, 12...Speaker, 13, 14, 15, 16
...Chain sound pause section, 17, 18, 19, 2
0...Alarm starts ringing, 21, 22, 23, 2
4...1/2 frequency divider circuit, 25, 26...AND circuit, 27
...OR circuit, 28...NOT circuit, 29...1/2 frequency divider circuit with data input, 30...NOT circuit, 31,3
2, 33...NAND circuit, 34...AND circuit, S ₁ ...
8Hz signal of analog section, S ₂ ... 4Hz signal of analog section, S ₃ ... 2Hz signal of analog section, S ₄ ... 1Hz signal of analog section, S ₅ ... alarm start trigger signal,
_S6 ...1Hz differential signal of digital section, _S7 ...16Hz signal of analog section, _S8 ...reset signal of analog section,
S ₉ ...Alarm match signal, S ₁₀ ...Alarm sounding command signal.

Claims (1)

[Claims] 1. An oscillation circuit that outputs a reference signal, a first frequency divider circuit that divides the frequency of the reference signal from the oscillation circuit, and a second frequency divider that receives the output signal from the first frequency divider circuit and divides the frequency of the analog part. frequency dividing circuit, a motor drive circuit that inputs the output signal from the second frequency dividing circuit and outputs a motor drive signal for driving the motor, inputs the output signal from the first frequency dividing circuit, and divides the frequency of the digital part. a third frequency dividing circuit that inputs an alarm sound command signal and generates an alarm sound with a pause period in which no sound is produced; The alarm control circuit has an alarm control circuit that outputs an alarm sound command signal to generate an alarm sound, and the alarm control circuit inputs the output signal from the second frequency dividing circuit, and the alarm control circuit inputs the output signal from the second frequency dividing circuit, and sets the pause period provided for the alarm sound to the motor. A first gate circuit that outputs an alarm start trigger signal to match the drive signal, and an alarm start trigger signal from the first gate circuit and a time signal based on the third frequency dividing circuit are input, and the alarm start signal is output. A second gate circuit to output, an alarm start signal from the second gate circuit, and an alarm coincidence signal based on the third frequency divider circuit are input, and the alarm coincidence signal is delayed by the alarm start signal. 1. An alarm control circuit for a composite electronic timepiece, comprising: a third gate circuit that outputs an alarm sounding command signal.