JPH1165538A - Display controller/driver ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display controller/driver IC the power consumption of which is lowered and the performance of which is made high. SOLUTION: An oscillation circuit 1 generates a reference clock whose frequency is nHZ ((n)is an arbitrary natural number), frequency-dividing circuits 2, 3 frequecy-divide a reference signal, a gradation forming circuit 4 outputs a signal having a prescribed frequency by inputting imput signals A, B from the frequency-dividing circuits 2, 3 and a gradation control signal 30 controlling the number of gradations. In this output, the frequency nHz of the reference clock is made switchable by the number of gradations controlled by the gradation control signal 30. Consequently, the reference clock of the oscillation circuit 1 can be lowered by the gradation control signal or of gradation number changeover signal. Thus, the lowering of the power consumption is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display controller / driver IC, and more particularly, to a display controller / driver IC with gradation.

[0002]

2. Description of the Related Art Conventionally, display controller / driver ICs
Is generally configured as an IC having an oscillation circuit and a frequency dividing circuit. For example, FIG. 6 is a block diagram showing a circuit configuration example of a conventional general display controller / driver IC. I of the conventional display controller / driver IC
The C block includes an oscillation circuit 17 for generating a reference clock.
And 1/2 frequency dividers 18 and 19 for dividing the reference clock
And a gradation generation circuit 20 that switches the output pulse width to generate a gradation.

FIG. 7 shows a waveform example of each part in FIG. For example, it is now possible to display five shades (5 gradations)
Consider a display controller / driver IC. That is, 1
The output pulse width 21 can be controlled in units of / 4, and 5 of 0/4 (no output pulse), 1/4, 2/4, 3/4, 4/4
Use stages. In order to control the output pulse width 21, an nHz clock 24 having an oscillation frequency, a 1 / 2nHz clock 23 of a B clock obtained by dividing the frequency by 1/2, and a 1 / 4nHz clock 22 of an A clock obtained by dividing the frequency by 1/2
Use These A clock, B clock and gradation control signal 32 are used as input signals, and output pulse 2
One pulse width can be switched to each width indicated by a dotted line.

In the above-mentioned conventional display controller / driver IC, the reference clock is fixedly set to the maximum number of gradations. For example, even when only three gradations of 0, 2/4, and 4/4 are used, a reference clock having a maximum clock of nHz is used. Therefore, frequency switching is performed in a high frequency region even when the number of gradations is reduced.

[0005]

However, the display controller / driver IC of the above-described conventional example consumes 5 power even when the number of gray levels is reduced, for example, when 5 gray levels are changed to 3 gray levels. There is a problem that is not substantially different from the case of gradation.

It is an object of the present invention to provide a display controller / driver IC with reduced power consumption and improved performance.

[0007]

In order to achieve the above object, a display controller / driver IC of the present invention is connected to a gradation control signal for controlling the number of gradations and outputs a reference clock nHz (n is an arbitrary natural number). An oscillation circuit that generates the frequency, a frequency dividing circuit that divides the reference clock, and a gradation generating circuit that receives the output signal of the frequency dividing circuit and the gradation control signal as input signals and outputs a signal of a predetermined frequency. And the number of gradations controlled by the gradation control signal,
It is characterized in that the frequency nHz of the reference clock can be switched.

Further, the frequency dividing circuit is constituted by a plurality of stages of at least two circuits, the frequency dividing operation of each frequency dividing circuit can be controlled by the number of gradations, and the frequency dividing circuit can be controlled by the maximum number of gradation levels to be used. The frequency nHz at which the oscillation circuit oscillates can be changed, and when the number of gradation levels is reduced, the frequency nHz of the reference clock may be reduced.

Further, the above-mentioned display controller / driver IC is configured such that a gradation switching signal for setting a maximum gradation level to be used is connected as an input signal. It is better to decide in advance whether to do so.

It is to be noted that the number of gradations is set as the minimum number of stages desired, the frequency nHz of the reference clock is reduced according to the set number of gradations, the operation of the unused frequency divider is stopped, and the power consumption is reduced. It is better to reduce it.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a display controller / driver IC according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 5, there is shown an embodiment of a display controller / driver IC of the present invention.
1 to 3 show a first embodiment, FIG. 4 shows a second embodiment,
FIG. 5 is a graph of a characteristic example of power consumption when the present embodiment is applied to a display controller / driver IC actually commercialized.

<First Embodiment> Referring to FIG. 1, a display controller / driver I according to a first embodiment of the present invention is described.
C has an oscillation circuit 1 that generates a reference clock having a frequency of nHz, 分 frequency divider circuits 2 and 3, and a gradation generation circuit 4. The gradation control signal 30 is output from the oscillation circuit 1/1 /
It is input to the divide-by-2 circuit 3 and the gradation generation circuit 4. Since the display controller / driver IC of this configuration is an example of five gradations, the 1/2 frequency dividing circuit has two stages. However, the number of stages of the 1/2 frequency divider circuit increases or decreases depending on the number of gradations.
0 is input as needed.

Next, an operation example of this embodiment will be described in detail with reference to FIGS. 1, 2 and 3. Frequency nH
The z reference clock 8 is generated by the oscillation circuit 1 and is input to the first-stage 分 frequency dividing circuit 2. The 1/2 frequency dividing circuit 2
A 1/2 nHz clock is generated and input to the grayscale generation circuit 4 as a B clock 7. Further, the ｎnHz clock is input to the １ ／ frequency dividing circuit 3 in the next stage, and １ ／ nH
The z-clock is generated and the A-clock 6 is generated as the gradation generation circuit 4
Is input to The number of gradation steps can be set to 1 /
The same circuit as the divide-by-2 circuit 3 is added.

When five gradations are considered, the width of the output pulse takes five values of 0, 1/4, 2/4, 3/4, and 4/4. The gradation generation circuit 4 uses the A clock 6 and the B clock 7 to generate 1/4 P of the output pulse width of these five gradations.
An output pulse of WM (pulse width modulaition) is generated and output. The output pulse (1/4 PWM) 5 has five gradation levels of the output pulse. For the gradation "0", a flat signal of 0 level is used, and for the gradation "1/4", the pulse width is 50 to 50.
51, a pulse width of 50 to 52 for gradation "2/4", a pulse width of 50 to 53 for gradation "3/4", and a gradation of "4 /
In the case of "4", the pulse width is 50 to 54.

The frequency of the reference clock in the case of the five gradations is nHz. The case where the frequency of the reference clock is semi-fixedly controlled by the number of gradations set by the gradation control signal 30 will be described below. However, irrespective of the number of gradations, it is also possible to operate with the frequency of the reference clock variable according to the control signal of the gradation control signal. This is related to the number of gradations and the dynamic range.

A case where only three gradations are used under the control of the gradation control signal 30 will be considered. There are three types of output pulse widths used: 0, 2/4, and 4/4. In this case, the timing waveform is as shown in FIG. That is, the oscillation circuit 1 switches to the mHz clock 11 which is half the frequency of the nHz clock as the reference clock by the gradation control signal 30. Further, the 分 frequency dividing circuit 2 generates a ｍ mHz clock and inputs it as a B clock 10 to the gradation generating circuit 4. Gradation generation circuit 4
Is a 1/2 PWM output pulse 9 from the B clock 10.
Generate At this time, since the 1/2 frequency dividing circuit 3 is not necessary, the operation is stopped by the gradation control signal 30. The frequency of the reference clock in the case of these three gradations is mHz. Note that the nHz clock 12 in FIG.
Posted for reference.

According to the first embodiment, when the number of gradations is reduced, the oscillation frequency of the reference clock is reduced. This makes it possible to reduce the power consumption of the oscillation circuit 1 and the 1/2 frequency dividing circuit 2. Also, by stopping unnecessary operation of the 1/2 frequency dividing circuit 3,
Power consumption can be reduced.

<Second Embodiment> Next, a second embodiment of the present invention will be described in detail with reference to FIG. FIG.
As shown in the figure, the basic form of the second embodiment is the same as that of the first embodiment. The difference is that the number of gradations to be used is previously determined by the gradation number switching signal.

Referring to FIG. 4, the display controller / driver IC according to the second embodiment includes an oscillation circuit 13, 1/2
It has frequency dividing circuits 14 and 15 and a gradation generating circuit 16. The gradation control signal 31 is input to the oscillation circuit 1, the 1/2 frequency dividing circuit 15, and the gradation generation circuit 16. The display controller / driver IC having this configuration is the first type.
This is an example of 5 gray scales as in the embodiment, and the 1/2 frequency dividing circuit has two stages. However, the number of stages of the 1/2 frequency dividing circuit is increased or decreased according to the number of gradations, and a gradation control signal 31 is input as needed for controlling the increase or decrease. Further, based on the gradation switching signal 40, the oscillation circuit 13 and the gradation generation circuit 16 determine how many gradations to use. Also,
Also for the 1/2 frequency dividing circuit 15, the gradation number switching signal 4
Use 0 to determine whether to use.

The waveforms of the respective parts are the same as in the first embodiment, and are shown in FIGS. 2 and 3.

In the display controller / driver IC according to the second embodiment, the gradation control signal 31 is also inputted to the oscillation circuit 13 and the 1/2 frequency dividing circuit 15, and the frequency of the reference clock is changed depending on the gradation to be used. The frequency is reduced and the 1/2 frequency dividing circuit 14 is not used. Therefore, the effect of the second embodiment is that the power consumption is reduced as in the first embodiment.

FIG. 5 shows the transmission frequency [KH] of the reference clock.
6] is a characteristic graph example showing a relationship between z] and power consumption [mW]. This graph shows the LCD controller / driver IC
(Product model of NEC Corporation; μPD16661A)
Is a measured value obtained by actually measuring the relationship between the oscillation frequency of the reference clock and the power consumption of the oscillation circuit unit. As is known from this characteristic graph example, the relationship between the reference clock (oscillation frequency) and the power consumption is almost proportional. In other words, the power consumption increases in proportion to the increase in the number of gradations. Conversely, when the number of gradations is reduced, the power consumption is reduced substantially in proportion to the number of gradations. As can be seen from the characteristic diagram 5, the reference clock nHz in the case of five gradations is changed to mHz in the case of three gradations.
, The power consumption is reduced to about ２.

Although the above embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. is there.

[0024]

As is clear from the above description, the display controller / driver IC of the present invention has a frequency of nHz (n
Generates an arbitrary natural number) reference clock and divides the frequency.
An input signal and an output signal to the frequency dividing circuit and a gradation control signal for controlling the number of gradations are input signals, and a signal of a predetermined frequency is output. In this control, the frequency nHz of the reference clock can be switched according to the number of gradations controlled by the gradation control signal. Therefore, the oscillation circuit or the reference clock can be reduced by the gradation control signal or the gradation number switching signal. As a result, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a display controller / driver IC of the present invention.

FIG. 2 is a waveform diagram of each part when FIG. 1 is used in five gradations.

FIG. 3 is a waveform diagram of each part when FIG. 1 is used in three gradations.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a graph showing an example of a relationship between an oscillation frequency of a reference clock and power consumption.

FIG. 6 is a block diagram of a conventional display controller / driver IC.

FIG. 7 is a waveform chart of each part of the conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 oscillation circuit 2 1/2 frequency divider 3 1/2 frequency divider 4 gradation generator 5 output pulse waveform 6 A clock waveform 7 B clock waveform 8 reference clock waveform (nHz clock) 9 output pulse waveform 10 clock B waveform 11 Reference Clock Waveform (mHz Clock) 12 Reference Clock Waveform (Reference, nHz Clock) 13 Oscillator 14 1/2 Divider 15 1/2 Divider 16 Gradation Generator 17 Oscillator 18 1/2 Divider Circuit 19 1/2 frequency dividing circuit 20 Tone generation circuit 21 Output pulse waveform 22 Clock A waveform 23 Clock B waveform 24 Reference clock waveform (nHz clock)

Claims (6)

[Claims] An oscillation circuit connected to a gradation control signal for controlling the number of gradations and generating a reference clock nHz (n is an arbitrary natural number); a frequency dividing circuit for dividing the reference clock; A grayscale generation circuit configured to output an output signal of a circuit and the grayscale control signal as an input signal and output a signal of a predetermined frequency, wherein the reference clock is determined by the number of grayscales controlled by the grayscale control signal. A display controller / driver IC, wherein the frequency nHz can be switched. 2. The frequency dividing circuit according to claim 1, wherein the frequency dividing circuit is configured in a plurality of stages of at least two circuits, and the frequency dividing operation of each of the frequency dividing circuits can be controlled by the number of gradations. Display controller / driver IC. 3. Depending on the number of maximum gradation levels used,
3. The display controller / driver IC according to claim 1, wherein a frequency nHz at which the oscillation circuit oscillates can be changed. 4. When the number of gradation levels is reduced,
4. The display controller / driver I according to claim 3, wherein the frequency nHz of the reference clock is reduced.
C. 5. The display controller / driver IC
Is further configured such that a gradation switching signal for setting the maximum gradation level to be used is connected as an input signal,
5. The display controller / driver IC according to claim 3, wherein the number of gradations to be used is determined in advance by the gradation number switching signal. 6. A method of setting the number of gradations as a desired minimum number of steps, lowering the frequency nHz of the reference clock according to the set number of gradations, and stopping the operation of an unused frequency dividing circuit; 3. The power consumption is reduced.
6. The display controller / driver IC according to any one of items 1 to 5.