JPS5917726A - Programmable frequency generator for inverter driving having inductive load - Google Patents

Abstract

PURPOSE:To increase the number of degrees of freedom for frequency division ratio and reduce the burden of software, by using the frequency division due to a microcomputer for a relatively low-frequency part when a frequency is generated by a programmable frequency generator. CONSTITUTION:A frequency fOSC generated from a reference frequency oscillator 1 is inputted to a programmable counter 2, and the frequency which can be followed by a microcomputer 3 synthesized by the frequency division due to software of the microcomputer 3. The output of the programmable counter 2 is outputted directly to combine this frequency and a frequency range higher than this frequency, and the cascade connection circuit of the programmable counter 2 and a binary counter 4 is constituted equivalently, and a frequency to be applied to an inverter having an inductive load is synthesized. Consequently, the software frequency division ratio can be set to an optional integer to increase the number of degrees of freedom for frequency division ratio in comparison with the use of the binary counter, and a software timer is used only at the inverter start time to reduce the burden of software.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a programmable frequency generator for driving an inverter with an inductive load, such as a variable speed air conditioner compressor motor.

Conventional configurations and their problems Traditionally, in order to configure a programmable timer with a wide frequency division ratio, it is necessary to use a wide range of frequency division ratios as shown in Figure 1, or to use a low-bit programmable timer as shown in Figure 2. A method using a cascade connection of a counter and a binary counter is known. Incidentally, the frequency output divided by the programmable counter is expressed by the following equation.

Here, fO5c is the reference oscillator input, fOUT is the frequency output, n is the frequency division ratio, and a is the number of address bits of the programmable counter.

FIG. 1 is an example in which the number a of address bits in the above formula is increased.

In the circuit of FIG. 1, a reference oscillator 1 generates a frequency, fosc, which is input to a programmable counter 2.

On the other hand, from the output terminals 0 to 0- of the microcomputer 3, the programmable counter 2 outputs A0 (-1) of the output terminal P. A binary address code is set in -P(a-1). fOUT is an output terminal frequency-divided by fO8ck.

Here, if the number of address bits is ai8, the frequency division ratio n is 1
256, and if the number of address bits ai is 10, then the division ratio n is 1 to 1023, and if the number of address bits is a', 5) 12, the division ratio n is 1 to 4.
o96, and the desired purpose can be achieved by appropriately selecting the number of address bits a, but this structure is difficult because there are no multi-bit programmable counters on the market, and the number of address outputs of the microcomputer is limited. This has disadvantages such as increased number of users and complicated software.

Next, the structure shown in FIG. 2 will be explained.

In the figure, 1.2.3 is the same reference oscillator as in Figure 1,
A programmable counter and a microcomputer are shown, and 4 is a binary counter section with several stages. The output fOUT of this circuit is the output of each stage of the binary counter section 4 and is connected to the output terminal ○ of the microcomputer 3. 1-0. □
The output selection unit 6 selects and outputs the output using the .

- For example, if the programmable counter 2 has 8 bits and f03o/600 is required as the output fOUT, the frequency division range of the programmable counter 2 is the division ratio n from 1 to 25.
5, so its output is fOUT-, fO3C/'c1
6ox22).

Therefore, the output terminal 07-0 of the microcomputer 3
The address code output from ゜ is 10010110, which is the output terminal ○ of the microcomputer 3. (x-2
) is set to "H". Although this method has the advantage that the frequency division ratio can be arbitrarily created to some extent and can be configured using general-purpose ICs on the market, it is not practical because it requires a large number of parts and occupies many output terminals of the microcomputer.

OBJECTS OF THE INVENTION The present invention aims to overcome the drawbacks of the prior art as described in section 2.
C'f: The purpose is to create a programmable counter with a simple circuit configuration that does not place a large burden on the software of the microcomputer and does not occupy many unused output terminals.

Structure of the Invention The present invention synthesizes frequencies in a range that can be sufficiently tracked by a microcomputer by frequency division using software of the microcomputer, and directly outputs the output of a programmable counter in a frequency range above that frequency. This is an isometric configuration of a cascade circuit of a binary counter and a binary counter, and synthesizes the frequency applied to an inverter with an inductive load. The degree of freedom is increased, and a software timer is used only when the inverter is started, thereby minimizing the burden on the software.

Hereinafter, as an embodiment of the present invention, the configuration of a PWM type original oscillator circuit for a room air conditioner inverter will be described with reference to FIG. Here, the PWM method is an abbreviation for pulse width modulation method, and is a method in which a voltage chiyono-pink algorithm is configured so that the integral value over time of the voltage applied to the inverter approximates a sine wave.

In the figure, 1 is a reference frequency generator that does not generate the reference frequency f but SC, 2 is a general-purpose programmable counter with a built-in binary counter, 3 is a p-MOS microcomputer, and 4 is a binary counter built in the programmable counter 2. Counter, 6-digit output frequency range data f1. This is a selection output circuit that switches and outputs f2 and f3.

In the above configuration, the frequency fosc generated by the reference frequency oscillator 1 is input to the CLK terminal of the programmable counter 2, and the address input P is inputted to the CLK terminal of the programmable counter 2. The rear address code is inputted from the outputs O8 to P7 of the microcomputer 3 to P7, and the frequency division ratio is determined.

The direct output of programmable counter 2 is fl,
The output of the binary counter 4 built into the programmable counter 2 is f2, and this output f2 is input to the interrupt input I0 of the microcomputer 3. The output f2 is frequency-divided by the software of the microcomputer 3, and the final frequency output fOUT is output from the output terminal -○ of the microcomputer 3 depending on the frequency range. It is selectively outputted through the selective output circuit 5 designated by 1 to 003. Here f 1= fosc/n
(n = 1-265).

f2=f()3 c/(2Xn) (n=1-255
) rf3=f□SC/(2XnXm) (n=1-266
, m=1.2.3...). By the way, D is the address input of programmable counter 2 (P0 to P7
) is added to /(inary coat), and m is a frequency division ratio determined by the software of the microcomputer 3.

Here, the microcomputer 3 usually has other system systems (goods) as well, and the speed cannot be so high, so the output f2 when outputting the output f3 needs to be set to a relatively low frequency. The PWM system for air conditioner inverters usually uses the synchronous frequency f of the motor. In many cases, total oscillation is obtained by multiplying
As shown in the figure. The one shown in the same figure is 42, -fO8 in the carrier.
C-320''-, the frequency output range is converted to a synchronous frequency and output as 2 to 90Hz in IHz steps.In the division ratio column, the first term on the left, 85 to 254, is a programmable counter. The frequency division ratio, the second term 2, indicates the output designation of the binary counter attached to the programmable counter, and the third term, the multiplier of 2, indicates the frequency division ratio determined by the software of the microcomputer.

Here, the normal operating range for an air conditioner is 30 to 90Hz converted to the synchronous frequency of the motor.The 3oHz non-drip frequency is used only at startup, so the motor is on the normal rotation side @
While receiving the data, the microcomputer only needs to specify the address and specify the output of fl.

Furthermore, from Fig. 4, when f3 is output (is the maximum value of the frequency manually input to the microcomputer, fO8c/(2X1
36) -1 = 1.1 kt (about z), which is a value that even a commercially available 4-bit microcomputer can follow and process. That's about 30 microcomputers. is interrupted manually, t,−,4
If so, use a software timer to output f3'
c- Can also be synthesized. In this case as well, the negative phase of the software is small since it is only at the time of starting.

Additionally, if the load is an inverter that drives a compressor motor for an air conditioner, if the target frequency is suddenly applied, an inrush current that is more than three times that of the steady state will flow, and if the applied frequency suddenly changes, the compressor may lock or reverse. Inconveniences arise, such as the electromotive force causing damage to the power elements constituting the inverter.

Therefore, the present invention implemented a frequency change pattern shown in FIG. 5 as an example. That is, when the set frequency 1 is set, the output frequency fOUT monotonically increases in stages as shown in FIG. Next, when setting frequency 2 is set to a lower value than setting frequency 1, the frequency decreases monotonically with setting frequency 2 as the target.

One step in this stage is set to correspond to IHz of the periodic speed of the motor based on the embodiment shown in FIGS. 3 and 4, for example. Since the inrush current of a motor is proportional to the applied voltage, in the PWM system, the lower the applied frequency, the lower the inrush current.

Therefore, by changing the frequency as shown in FIG. 5, the starting current of the motor is suppressed, sudden changes in the load on the knob/knob are suppressed, and smoother rotation becomes possible.

Effects of the Invention According to the present invention, when a programmable frequency generator generates an arbitrary frequency, the relatively low frequency part is divided by a microcomputer, so that
The frequency division ratio of the system can be freely changed without increasing the number of component parts, and since frequency division processing in software is only done when starting the motor, the burden is extremely low.As a result, basic programmability The counter can be configured with a general-purpose, inexpensive counter, which provides a great cost advantage.Also, the frequency division ratio by software can be set to 1/integer, compared to conventional programmable counter and binary counter configurations. This increases the degree of freedom in the frequency division ratio, and when using interrupt input, the burden on the software is simply specifying the frequency division and selecting the output, so it is much simpler than using a multi-bit programmable counter. 76
The frequency can be changed gradually with high resolution,
This has various advantages, such as smoother motor control.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a programmable timer showing different conventional examples, FIG. 3 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention, and FIG. 4 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention. An explanatory diagram showing a specific design example, and FIG. 5 is a timing chart showing frequency changes by the programmable frequency generator. 1... Reference frequency generator, 2... Programmable counter, 3... Microcomputer, 4... Binary counter, 5... River selection output circuit . Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] Consisting of a programmable counter with an address input and a microcomputer with a selection output, the address input of the programmable counter is operated by the microcomputer, the output of the programmable counter is taken into the input terminal of the microcomputer, and branching is performed. By setting a fixed frequency as the frequency, setting a frequency above the branch frequency as a regularly used range, setting a range below the branch frequency as a starting range, and switching the selection output of the microcomputer, the program counter is set in the normally used range. In the starting region, the output of the programmable counter is divided by the software of the microcomputer, and the output frequency is increased or decreased in steps until the target frequency is reached. A programmable frequency generator for driving an inverter with an inductive load.