JPS5916427A - Programmable frequency generator - Google Patents

Abstract

PURPOSE:To improve the degree of freedom of a frequency dividing ratio, by using a divided frequency by means of a microcomputer for a comparatively low frequency, in generating an optional frequency at a programmable frequency generator. CONSTITUTION:A frequency fosc generated from a reference frequency oscillator 1 is inputted to a CLK terminal of a programmable counter 2, and an address code is inputted from outputs O0-O7 of the microcomputer 3 to address inputs P0-P7 to determine the frequency dividing ratio. A direct output of the counter 2 is f1 and an output of a binary counter 4 incorporated in the counter 2 is f2 and it is inputted to an interruption input I0. An output frequency-dividing the output f2 with the software of the computer 3 is f3 and the final frequency output fOUT is outputted selectively via a selecting output circuit 5 designated at output terminals O01-O03 of the computer 3 with the frequency range.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a programmable frequency generator for applications in motor vehicles with inductive loads, such as variable speed compressor motors for air conditioners.

Conventional configurations and their problems Traditionally, in order to configure a programmable timer with a wide frequency division ratio, it is necessary to use a wide range of frequency division ratios as shown in Figure 1, or to use a low-bit programmable timer as shown in Figure 2. A method using a cascade connection of a counter and a binary counter is known. Incidentally, the frequency output divided by the programmable counter is expressed by the following equation.

fOUT=㉟(n=1~(2”-1)) where fO8
c is the reference oscillator input, foUT is the frequency output, n is the frequency division ratio, and a is the number of address bits of the programmable counter.

FIG. 1 is an example in which the number a of address bits in the above formula is increased.

In the circuit shown in FIG. 1, a reference oscillator 1 generates a frequency fosc, which is input to a programmable counter 2. On the other hand, the output terminal 60~Φ(a-1) of the microcomputer 3
The address of the programmable counter 2 is P. −
A binary address code is set in P(a-1). foUT is an output terminal obtained by frequency-dividing foSC.

Here, if the number of address bits is ai8, the frequency division ratio n is 1
~266, and if the number of address bits a is still 1o, the division ratio n will be 1 to 1o23, and if the number of address bits a is 12, the division ratio n will be 1 to 4o96, and thus the number of address bits will be Although it is possible to achieve the desired purpose by appropriately selecting a, this structure is difficult because there are no multi-bit programmable counters on the market, and the number of address outputs from the microcomputer increases, making the software complicated. It has disadvantages such as.

Next, we will explain the structure of Fig. 2. In the same figure, 1.2.3 is the same reference oscillation unit as in Fig. 1;
A programmable counter and a microcomputer are shown, and 4 is a binary counter section with several stages. The output fOUT of this circuit is the output of each stage of the binary counter section 4, and the output Φ of the microcomputer 3. 1~Φ. The output selection unit 5 selects and outputs the output using a mechanical process.

As an example, if the programmable counter 2 has 8 bits and fosc/600 is required as the output fOUT, the frequency division range of the programmable counter 2 is the frequency division ratio n from 1 to 255, so the output is fOUT - fO8c/(150 x 22). becomes.

Therefore, the output terminals Φ7 to Φ of the microcomputer 3
. The address code output from is 1001011o, which is the output terminal ○ of the microcomputer 3. (x-2
) is set to "H". Although this method has the advantage that the frequency division ratio can be arbitrarily created to some extent and can be configured using general-purpose ICs on the market, it is not practical because it requires a large number of parts and occupies many output terminals of the microcomputer.

Purpose of the Invention The present invention aims to overcome the above-mentioned drawbacks of the conventional IC.
The purpose of this invention is to obtain a programmable counter with a simple circuit configuration without placing a large burden on the software of a microcomputer and without occupying many output terminals.

Structure of the Invention The present invention synthesizes frequencies in a range that can be tracked sufficiently by a microcomputer by frequency division using software of the microcomputer, and synthesizes frequencies in a frequency range higher than that frequency using a programmable counter of 141! By directly outputting the force, the cascade connection port F of the programmable counter and the binary counter is configured equally (1'5), and the software frequency division is set to an arbitrary integer. It is a higher value.

DESCRIPTION OF EMBODIMENTS J2+ Below, as an embodiment of the present invention, the structure of a PWM type original oscillation circuit of an inverter for a room air conditioner is described in the third section.
This will be explained using figures. The PWM method is an abbreviation for pulse width modulation method, and is a method in which a voltage chopping algorithm is configured so that the integral value over time of the voltage applied to the inverter approximates a sine wave.

In the figure, 1 is a reference frequency generator that generates a reference frequency fO8c, 2 is a general-purpose programmable counter with a built-in binary counter, 3 is a P-MOS microcomputer, 4 is a binary counter built in the programmable counter 2, 5 is the data f1.5 depending on the output frequency range. This is a selection output circuit that switches and outputs f2 and f3.

In the configuration described in item 1, the frequency fosc generated by the reference frequency oscillator 1 is the CLK of the programmable counter 2.
The output Φ of the microcomputer 3 is input to the terminal and sent to addresses P0 to P7. An address code is input from ~d7, and a frequency division ratio is determined. Programmable counter 2
The direct output of is fl, the output of the pinary counter 4 built into the program counter 2 is f, and this output f
2 is Micro 2 Combita 3 interrupt human power. has been entered.

The output obtained by dividing the frequency of the output f by the software of the microcomputer 3 is f3, and the final frequency output fOUT
is the output terminal Φ of the microconbeater 3 depending on the frequency range. It is selectively outputted through the selective output circuit 5 designated by 1 to '03.

Here f1=foBc/n (n-265) J f2
=f□Bc/(2xn)(n=1-255), f3=f
O8c/(2xnxm)(n-1~255.m=1.2
．． 3...). Incidentally, n is a binary code added to the address input (Po to P7) of the programmable counter 2, and m is a frequency division ratio determined by the software of the microcomputer 3.

Here, the microcomputer 3 usually has other system control functions and cannot operate at a very high speed, so the output f2 must be set at a relatively low frequency when the output f3 is output.

The PWM method of inverters for room air conditioners often uses the synchronous frequency f0 of the motor multiplied by a carrier as the primary oscillation, but here we will explain the calculation results of one example in the fourth section.
As shown in the figure. The one shown in the same figure has a carrier of 42, fosc
= 320 KHz, and the frequency output range is converted into a synchronous frequency, which can be output in IHz steps as 2 to 90 Hz. In the frequency division ratio column, the first term 86 to 254 on the left side is the programmable counter frequency division ratio, the second term 2 is the output specification of the binary counter attached to the programmable counter, and the third term multiplier of 2 is the microcomputer software. It shows the frequency division ratio.

From Figure 4, when outputting f3, the maximum value of the frequency input to the microcomputer is f□sc/(2x136)i
, about IKHz, which is a value that can be fully followed and processed by a commercially available 4-bit microcomputer technology. Also, input T of microcomputer 3. If S is not an interrupt input, output f3 can be synthesized using a software timer.Here, if the load is an inverter that drives a compressor for an air conditioner, set the target frequency. If applied suddenly, an inrush current three times or more than the steady state will flow, and if the applied frequency is suddenly changed, the compressor may lock or the back electromotive force may destroy the power elements that make up the inverter.

Therefore, the present invention implemented a frequency change pattern shown in FIG. 5 as an example. That is, when the set frequency 1 is set, the output frequency fo'UT monotonically increases in stages as shown in FIG. Next, when setting frequency 2 is set to a value lower than setting frequency 1, the frequency decreases monotonically with setting frequency 2 as the target.

One step in this stage is set to, for example, 1f (equivalent to z) of the periodic speed of the motor based on the embodiment shown in Figs. 3 and 4. Since the inrush current of the motor is proportional to the applied voltage, the PWM method The lower the applied frequency, the lower the inrush current.

Therefore, by changing the frequency as shown in FIG. 6, the starting current of the motor is suppressed, sudden changes in the load of the compressor are suppressed, and smooth rotation control becomes possible.

In this embodiment, the PWM method of an inverter for a room air conditioner has been described, but the present invention can be similarly implemented for applications requiring frequencies with a wide dynamic range, such as melody synthesis.

Effects of the Invention According to the present invention, when a programmable frequency generator generates an arbitrary frequency, a relatively low frequency portion is divided by a microcomputer, so that
It is possible to freely change the frequency division ratio of the system without increasing the number of component parts, and as a result, the basic programmable counter can be constructed from general-purpose, inexpensive items, resulting in a great cost advantage. In addition, since the frequency division ratio by software can be set to 1/integer, the degree of freedom in the frequency division ratio is higher compared to the conventional configuration of a programmable counter and a binary counter. When using , all you have to do is specify the frequency division and select the output, so it is much simpler than using a multi-bit programmable counter, and the frequency can be changed gradually with high resolution. This has various advantages such as smoother motor control.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of a programmable timer showing different conventional examples, FIG. 3 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention, and FIG. 4 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention. An explanatory diagram showing a specific design example, and FIG. 5 is a timing chart showing frequency changes by the programmable frequency generator. 1... Reference frequency generator, 2... Programmable counter, 3... Microcomputer, 4... Binary counter, 5...
・Selection output circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 178Mt. 133--

Claims (1)

[Claims] Consisting of a programmable counter equipped with an address input and a microcomputer equipped with a selection output, the address input of the programmable counter is operated by the microconbeater, and the output of the programmable counter is input to the input terminal of the microcomputer. By setting a fixed frequency as the branching frequency and switching the selection output of the microcomputer, the output of the program counter is output as is in the frequency range above the branching frequency and up to the upper limit frequency, and in the frequency range below the branching frequency. and a programmable frequency generator that outputs the output of the programmable counter by frequency division by software of the microcomputer in the frequency range up to the lower limit frequency, and increases or decreases the output frequency in steps until the target frequency is reached.